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1. 发明授权

US4632909A Monoclonal antibodies which block infectivity of malarial parasites to mosquitoes 失效
标题翻译：阻止疟疾寄生虫感染蚊子的单克隆抗体
公开(公告)号：US4632909A
公开(公告)日：1986-12-30
申请号：US547235
申请日：1983-10-31
申请人： Richard Carter , Louis H. Miller
发明人： Richard Carter , Louis H. Miller
IPC分类号： A61K38/00 , C07K16/20 , G01N33/536 , A61K39/395 , C12N5/00 , C12P21/00
CPC分类号： C07K16/205 , A61K38/00
摘要： Monoclonal antibodies have been developed that bind with one or more proteins located on the surface of gametes or zygotes of malaria parasites. These antibodies are specific for antigens on mosquito midgut stages of malaria parasite and sterilize the parasites in mosquitoes otherwise capable of transmitting the disease. The monoclonal antibodies are specific for the 255, 59 and 53 kilodalton surface proteins on Plasmodium falciparum and for the 25 kilodalton surface protein on zygotes and ookinetes of Plasmodium gallinaceum.
摘要翻译：已经开发了与位于配子或疟原虫合子表面的一种或多种蛋白质结合的单克隆抗体。这些抗体对疟疾寄生虫的蚊子中肠阶段的抗原是特异性的，并且对蚊子的寄生虫进行消毒，否则能够传播该疾病。单克隆抗体对恶性疟原虫上的255,59和53千道尔顿表面蛋白是特异性的，对于镰刀菌的合子和卵母细胞的25千道尔顿表面蛋白是特异性的。

2. 发明申请

US20140315017A1 GROUND COVER FOR CONTAINMENT BARRIERS 有权
公开(公告)号：US20140315017A1
公开(公告)日：2014-10-23
申请号：US14043708
申请日：2013-10-01
申请人： Richard Carter
发明人： Richard Carter
IPC分类号： E02D3/00
CPC分类号： E02D31/004 , E02D3/005 , Y10T428/249921 , Y10T428/273
摘要： A ground cover for use as a containment barrier including a geomembrane sheet and a geotextile sheet bonded together by an adhesive layer positioned therebetween. The adhesive layer does not fully cure, remains tacky and has an adhesive strength sufficient to maintain a bond between the geomembrane sheet and the geotextile sheet under normal foot traffic and a release point allowing separation of the geomembrane sheet and the geotextile sheet under shear forces generated by heavier traffic.

3. 发明授权

US08835245B2 Semiconductor device comprising self-aligned contact elements 有权
标题翻译：包括自对准接触元件的半导体器件
公开(公告)号：US08835245B2
公开(公告)日：2014-09-16
申请号：US13372604
申请日：2012-02-14
申请人： Peter Baars , Till Schloesser , Frank Jakubowski , Andy Wei , Richard Carter , Matthias Schaller
发明人： Peter Baars , Till Schloesser , Frank Jakubowski , Andy Wei , Richard Carter , Matthias Schaller
IPC分类号： H01L21/8234 , H01L21/768 , H01L21/285 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823475 , H01L21/28518 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L21/823437 , H01L29/66636 , H01L29/7848
摘要： When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.
摘要翻译：当形成复杂的半导体器件时，可以在替换栅电极结构的占位符材料之前形成自对准触点，将替代栅极方法与自对准的接触方式结合使用。

4. 发明授权

US08735240B2 CET and gate current leakage reduction in high-k metal gate electrode structures by heat treatment after diffusion layer removal 有权
标题翻译：扩散层去除后通过热处理在高k金属栅电极结构中的CET和栅极电流泄漏降低
公开(公告)号：US08735240B2
公开(公告)日：2014-05-27
申请号：US13455489
申请日：2012-04-25
申请人： Torben Kelwing , Martin Trentzsch , Boris Bayha , Carsten Grass , Richard Carter
发明人： Torben Kelwing , Martin Trentzsch , Boris Bayha , Carsten Grass , Richard Carter
IPC分类号： H01L21/8238
CPC分类号： H01L21/82345 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/3105 , H01L21/3115 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： When forming high-k metal gate electrode structures by providing the gate dielectric material in an early manufacturing stage, the heat treatment or anneal process may be applied after incorporating work function metal species and prior to capping the gate dielectric material with a metal-containing electrode material. In this manner, the CET for a given physical thickness for the gate dielectric layer may be significantly reduced.
摘要翻译：当通过在早期制造阶段提供栅极电介质材料来形成高k金属栅电极结构时，可以在加入功函金属物质之后并且在用含金属的电极封盖栅极电介质材料之前施加热处理或退火工艺材料。以这种方式，用于栅极电介质层的给定物理厚度的CET可以显着降低。

5. 发明授权

US08664057B2 High-K metal gate electrode structures formed by early cap layer adaptation 有权
标题翻译：通过早期盖层适应形成的高K金属栅电极结构
公开(公告)号：US08664057B2
公开(公告)日：2014-03-04
申请号：US13565970
申请日：2012-08-03
申请人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
发明人： Rohit Pal , Sven Beyer , Andy Wei , Richard Carter
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763 , H01L21/336 , H01L21/28 , H01L21/44 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823828
摘要： When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.
摘要翻译：当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是在暴露观察者电极材料的表面时实现。

6. 发明授权

US08647952B2 Encapsulation of closely spaced gate electrode structures 有权
标题翻译：密封间隔栅电极结构的封装
公开(公告)号：US08647952B2
公开(公告)日：2014-02-11
申请号：US12974037
申请日：2010-12-21
申请人： Peter Baars , Richard Carter , Andy Wei
发明人： Peter Baars , Richard Carter , Andy Wei
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L21/28512 , H01L21/823412 , H01L21/823425 , H01L21/823475 , H01L23/28 , H01L23/485 , H01L29/6656 , H01L29/66628 , H01L29/7834 , H01L29/7847 , H01L2924/0002 , H01L2924/00
摘要： Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.
摘要翻译：通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中相邻栅电极之间的间距被积极地缩放，并且其中可以利用自对准接触元件来避免通常与使用通常可获得的光刻技术形成的窄接触元件。一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构，然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤，随后在第二层上形成第三电介质材料的第三层，其中形成第三层还包括形成第一水平部分在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。

7. 发明申请

US20130277766A1 MULTIPLE HIGH-K METAL GATE STACKS IN A FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：多个高K金属栅堆叠在场效应晶体管中
公开(公告)号：US20130277766A1
公开(公告)日：2013-10-24
申请号：US13453596
申请日：2012-04-23
申请人： Torben Kelwing , Martin Trentzsch , Richard Carter
发明人： Torben Kelwing , Martin Trentzsch , Richard Carter
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/28185 , H01L21/28194 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6659
摘要： When forming sophisticated high-k metal gate electrode structures, the threshold voltage characteristics are adjusted on the basis of a well-established high-k dielectric material with an appropriate layer thickness, for instance by incorporating an appropriate metal species. Thereafter, further high-k dielectric materials may be deposited, typically with a greater dielectric constant, so as to define the final CET and physical thickness.
摘要翻译：当形成复杂的高k金属栅极电极结构时，阈值电压特性是基于具有适当层厚度的公认的高k电介质材料进行调整的，例如通过掺入适当的金属种类。此后，可以沉积更多的高k电介质材料，通常具有较大的介电常数，以便限定最终的CET和物理厚度。

8. 发明申请

US20120211808A1 FIN-TRANSISTOR FORMED ON A PATTERNED STI REGION BY LATE FIN ETCH 有权
标题翻译： FIN-TRANSISTOR通过最新的FIN ETCH形成在图案区域
公开(公告)号：US20120211808A1
公开(公告)日：2012-08-23
申请号：US13372837
申请日：2012-02-14
申请人： Andy Wei , Peter Baars , Richard Carter , Frank Ludwig
发明人： Andy Wei , Peter Baars , Richard Carter , Frank Ludwig
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823425 , H01L21/823431 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L29/1045 , H01L29/165 , H01L29/41783 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/66575 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.
摘要翻译：当形成复杂的半导体器件时，与平面晶体管组合的三维晶体管可以通过在早期制造阶段中形成半导体翅片（即，在形成浅沟槽隔离时）基于替代栅极接近和自对准接触元件而形成其中半导体翅片的最终电有效高度可以在提供自对准接触元件之后和在更换栅极接近期间被调整。

9. 发明申请

US20120193727A1 ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A GATE DIELECTRIC CAP LAYER MATERIAL PRIOR TO GATE DIELECTRIC STABILIZATION 有权
标题翻译：通过扩大栅极电介质层材料来调节放电晶体管的栅极电压以进行电介质稳定化
公开(公告)号：US20120193727A1
公开(公告)日：2012-08-02
申请号：US13444955
申请日：2012-04-12
申请人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
发明人： Richard Carter , Martin Trentzsch , Sven Beyer , Rohit Pal
IPC分类号： H01L27/088
CPC分类号： H01L21/823462 , H01L21/28176 , H01L21/28194 , H01L29/513 , H01L29/517
摘要： Sophisticated gate electrode structures may be formed by providing a cap layer including a desired species that may diffuse into the gate dielectric material prior to performing a treatment for stabilizing the sensitive gate dielectric material. In this manner, complex high-k metal gate electrode structures may be formed on the basis of reduced temperatures and doses for a threshold adjusting species compared to conventional strategies. Moreover, a single metal-containing electrode material may be deposited for both types of transistors.
摘要翻译：复杂的栅极电极结构可以通过在进行用于稳定敏感栅极介电材料的处理之前提供包括可能扩散到栅极电介质材料中的所需物质的覆盖层来形成。以这种方式，与常规策略相比，可以基于用于阈值调节物质的降低的温度和剂量来形成复杂的高k金属栅电极结构。此外，可以为两种类型的晶体管沉积单个含金属的电极材料。

10. 发明申请

US20070004191A1 Novel techniques for precision pattern transfer of carbon nanotubes from photo mask to wafers 有权
标题翻译：碳纳米管从光掩模到晶圆的精密图案转移的新技术
公开(公告)号：US20070004191A1
公开(公告)日：2007-01-04
申请号：US11298274
申请日：2005-12-08
申请人： Shiqun Gu , Peter McGrath , James Elmer , Richard Carter
发明人： Shiqun Gu , Peter McGrath , James Elmer , Richard Carter
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , B82Y10/00 , H01L21/32136 , H01L21/32139 , H01L51/0018 , H01L51/0048 , Y10S977/742
摘要： A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer) Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using Cl, F plasma) the portions of the hard mask which have been already partially etched away.
摘要翻译：一种用于在晶片上图案化CNT的方法，其中CNT层设置在基板上，硬掩模膜沉积在CNT层上，BARC层（可选）涂覆在硬掩模膜上，并且抗蚀剂在 BARC层（或直接在硬掩模膜上，如果不包括BARC层）。然后，通过蚀刻BARC层（如果提供）并且部分地蚀刻到硬掩模膜上而不是完全通过硬掩模膜（即，在到达CNT层之前停止蚀刻），将抗蚀剂图案有效地转移到硬掩模膜。然后，剥离抗蚀剂和BARC层（如果提供），并且通过蚀刻掉（优选通过使用Cl，F等离子体）已经部分蚀刻掉的硬掩模的部分，将硬掩模图案有效地转移到CNT。

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