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    • 4. 发明授权
    • Encapsulation of closely spaced gate electrode structures
    • 密封间隔栅电极结构的封装
    • US08647952B2
    • 2014-02-11
    • US12974037
    • 2010-12-21
    • Peter BaarsRichard CarterAndy Wei
    • Peter BaarsRichard CarterAndy Wei
    • H01L21/336
    • H01L27/092H01L21/28512H01L21/823412H01L21/823425H01L21/823475H01L23/28H01L23/485H01L29/6656H01L29/66628H01L29/7834H01L29/7847H01L2924/0002H01L2924/00
    • Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.
    • 通常,本文公开的主题涉及复杂的半导体器件及其形成方法,其中相邻栅电极之间的间距被积极地缩放,并且其中可以利用自对准接触元件来避免通常与 使用通常可获得的光刻技术形成的窄接触元件。 一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构,然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。 说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤,随后在第二层上形成第三电介质材料的第三层,其中形成第三层还包括形成第一水平部分 在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。
    • 7. 发明申请
    • Encapsulation of Closely Spaced Gate Electrode Structures
    • 密封栅电极结构的封装
    • US20120153398A1
    • 2012-06-21
    • US12974037
    • 2010-12-21
    • Peter BaarsRichard CarterAndy Wei
    • Peter BaarsRichard CarterAndy Wei
    • H01L27/092H01L21/8234H01L29/772H01L21/28
    • H01L27/092H01L21/28512H01L21/823412H01L21/823425H01L21/823475H01L23/28H01L23/485H01L29/6656H01L29/66628H01L29/7834H01L29/7847H01L2924/0002H01L2924/00
    • Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.
    • 通常,本文公开的主题涉及复杂的半导体器件及其形成方法,其中相邻栅电极之间的间距被积极地缩放,并且其中可以利用自对准接触元件来避免通常与 使用通常可获得的光刻技术形成的窄接触元件。 一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构,然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。 说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤,随后在第二层上形成第三电介质材料的第三层,其中形成第三层还包括形成第一水平部分 在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。
    • 9. 发明授权
    • Method of forming self-aligned contacts for a semiconductor device
    • 形成用于半导体器件的自对准触点的方法
    • US08927407B2
    • 2015-01-06
    • US13354739
    • 2012-01-20
    • Peter BaarsAndy WeiErik GeissMartin Mazur
    • Peter BaarsAndy WeiErik GeissMartin Mazur
    • H01L21/28
    • H01L21/76897H01L29/66545
    • Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.
    • 本文公开了一种形成用于半导体器件的自对准接触件的方法。 在一个示例中,该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极,其中每个栅电极具有位于栅电极上的栅极帽层,并执行至少一个蚀刻工艺以限定自身 在多个间隔开的牺牲栅电极之间的对准接触开口。 该方法还包括去除栅极盖层,从而暴露每个牺牲栅电极的上表面,在所述自对准接触开口中沉积至少一层导电材料,并去除至少一层导电材料的部分 其定位在自对准接触开口的外侧,从而限定位于自对准接触开口中的自对准接触件的至少一部分。
    • 10. 发明申请
    • Method of Forming Self-Aligned Contacts for a Semiconductor Device
    • 形成半导体器件的自对准触点的方法
    • US20130189833A1
    • 2013-07-25
    • US13354739
    • 2012-01-20
    • Peter BaarsAndy WeiErik GeissMartin Mazur
    • Peter BaarsAndy WeiErik GeissMartin Mazur
    • H01L21/28
    • H01L21/76897H01L29/66545
    • Disclosed herein is a method of forming self-aligned contacts for a semiconductor device. In one example, the method includes forming a plurality of spaced-apart sacrificial gate electrodes above a semiconducting substrate, wherein each of the gate electrodes has a gate cap layer positioned on the gate electrode, and performing at least one etching process to define a self-aligned contact opening between the plurality of spaced-apart sacrificial gate electrodes. The method further includes removing the gate cap layers to thereby expose an upper surface of each of the sacrificial gate electrodes, depositing at least one layer of conductive material in said self-aligned contact opening and removing portions of the at least one layer of conductive material that are positioned outside of the self-aligned contact opening to thereby define at least a portion of a self-aligned contact positioned in the self-aligned contact opening.
    • 本文公开了一种形成用于半导体器件的自对准接触件的方法。 在一个示例中,该方法包括在半导体衬底之上形成多个间隔开的牺牲栅电极,其中每个栅电极具有位于栅电极上的栅极帽层,并执行至少一个蚀刻工艺以限定自身 在多个间隔开的牺牲栅电极之间的对准接触开口。 该方法还包括去除栅极盖层,从而暴露每个牺牲栅电极的上表面,在所述自对准接触开口中沉积至少一层导电材料,并去除至少一层导电材料的部分 其定位在自对准接触开口的外侧,从而限定位于自对准接触开口中的自对准接触件的至少一部分。