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    • 4. 发明授权
    • CMOS tapered gate and synthesis method
    • CMOS锥形栅极及其合成方法
    • US06966046B2
    • 2005-11-15
    • US09841505
    • 2001-04-24
    • Brian W. CurranLisa Bryant LaceyGregory A. NorthropRuchir PuriLeon Stok
    • Brian W. CurranLisa Bryant LaceyGregory A. NorthropRuchir PuriLeon Stok
    • G06F17/50H01L21/82H03K19/096H03K19/20
    • G06F17/505
    • A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.
    • 高性能门库增加了锥形门。 改变堆叠器件的宽度以减少通过一些输入引脚的延迟。 例如在锥形NAND门中,NFET堆叠中的底部器件具有比顶部器件更宽的宽度,以牺牲较大的底部输入到输出引脚延迟为代价来实现较小的顶部输入以输出引脚延迟。 使用合成算法的方法将输入网络修改为栅极引脚连接,并与锥形栅极交换传统的非锥形栅极,以改善时序关键路径的延迟。 最新到达的门输入网络被互换,网络连接到顶针。 然后将栅极转换成锥形栅极,提供通过底栅输入(不是时序关键)的路径。
    • 5. 发明授权
    • Method and apparatus for reducing bus noise and power consumption
    • 降低总线噪声和功耗的方法和装置
    • US5572736A
    • 1996-11-05
    • US414554
    • 1995-03-31
    • Brian W. Curran
    • Brian W. Curran
    • G06F13/40G06F1/32
    • G06F13/4072Y02B60/1228Y02B60/1235
    • In a computer system comprising a plurality of subsystems, interconnected by a bus comprising bit drivers and bit receivers, data words are transmitted on the bus in the form of code words. The code words are formulated such that the number of bits of the bus which changes with the transmission of successive code words is minimized. A switching code, comprising one or more bits, defines a plurality of mapping codes and a data word to be transmitted is mapped by use of the mapping codes to a plurality of code words. One of the plurality of code words differing from a previously transmitted code word in the least number of bit positions is selected. The selected code words is transmitted, together with a switching code, identifying the mapping from which the transmitted code word was generated. At the receiving end of the bus, the switching code is decoded to identify the mapping used in creating the code word. Using the identified mapping, the original data word is recovered.
    • 在包括由包括位驱动器和位接收器的总线互连的多个子系统的计算机系统中,数据字以代码字的形式在总线上传送。 编码字被配置为使得随着连续代码字的传输而变化的总线的位数最小化。 包括一个或多个位的切换代码定义多个映射代码,并且将要发送的数据字通过使用映射代码映射到多个代码字。 选择与最少数量的位位置中的先前发送的代码字不同的多个代码字中的一个。 所选择的代码字与切换代码一起发送,识别生成发送的代码字的映射。 在总线的接收端,对切换代码进行解码以识别用于创建代码字的映射。 使用识别的映射,恢复原始数据字。
    • 7. 发明授权
    • Expandable memory having plural memory cards for distributively storing
system data
    • 可扩展存储器,具有用于分布式存储系统数据的多个存储卡
    • US5428762A
    • 1995-06-27
    • US850194
    • 1992-03-11
    • Brian W. CurranJoseph L. Temple, III
    • Brian W. CurranJoseph L. Temple, III
    • G11C5/00G06F13/16G06F13/40G06F13/38G06F13/42
    • G06F13/1694
    • An improved memory system and memory controller which permits simplified memory upgrades in the field. The system includes a memory board with multiple card sockets. As additional cards are added the data cables are distributed among the cards and the memory controller is programmed to coordinate the sequencing of the memory in the cards. Data is transferred between the cards and memory controller via distributively coupled cables. Control and address signals are provided to cards via wires embedded in the memory board from the memory controller. A repowering circuit on each card makes copies of the control and address signals which are sent to other cards through the embedded wires in the board. Data received by a card is stored in memory through steering logic and buffers.
    • 改进的存储器系统和存储器控制器,其允许在现场简化存储器升级。 该系统包括一个具有多个卡插槽的存储器板。 随着附加卡被添加,数据电缆分布在卡之间,并且存储器控制器被编程以协调卡中的存储器的排序。 数据通过分布式耦合电缆在卡和存储控制器之间传输。 控制和地址信号通过从存储器控制器嵌入存储器板中的线路提供给卡。 每个卡上的重新加电电路将通过板中的嵌入式电线发送到其他卡的控制和地址信号的副本。 由卡接收的数据通过转向逻辑和缓冲器存储在存储器中。
    • 9. 发明授权
    • Noise-immune pass gate latch
    • 无噪声通过门锁
    • US5939915A
    • 1999-08-17
    • US907346
    • 1997-08-06
    • Brian W. Curran
    • Brian W. Curran
    • H03K3/013H03K3/037H03K3/356H03K3/289
    • H03K3/037H03K3/013H03K3/356156
    • A non-buffered, noise-immune transmission gate latch for high performance applications is disclosed. The latch data input circuit contains an additional PFET for pulling up the gate of a transmission PFET and an additional NFET to pull down the gate of the transmission NFET to prevent the transmission gate from inadvertently opening when noise is coupled into the data input node. When data input voltage rises to Vdd+Vtp, the additional PFET begins to turn ON, and an inverted clock node is pulled above Vdd. The higher inverted clock node voltage is coupled to the gate of the transmission PFET and thereby prevents the transmission PFET from inadvertently turning ON. When data input voltage drops to -Vtn, the additional NFET begins to turn ON, and a clock node Is pulled below ground. The lower clock node voltage is coupled to the gate of the transmission NFET and thereby prevents the transmission NFET from inadvertently turning ON. Thus two additional transistors provide the necessary noise immunity.
    • 公开了一种用于高性能应用的非缓冲,无噪声的传输门锁。 锁存数据输入电路包含用于提升传输PFET的栅极和附加NFET的附加PFET,以将传输NFET的栅极拉下来,以防止当噪声耦合到数据输入节点时传输门不经意地打开。 当数据输入电压上升到Vdd + Vtp时,附加PFET开始导通,反相时钟节点被拉到Vdd以上。 较高的反相时钟节点电压耦合到传输PFET的栅极,从而防止传输PFET无意中导通。 当数据输入电压下降到-Vtn时,额外的NFET开始导通,时钟节点被拉到地下。 较低时钟节点电压耦合到传输NFET的栅极,从而防止透射NFET无意中导通。 因此两个额外的晶体管提供必要的抗干扰能力。