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US06966046B2 CMOS tapered gate and synthesis method 失效
标题翻译： CMOS锥形栅极及其合成方法
公开(公告)号：US06966046B2
公开(公告)日：2005-11-15
申请号：US09841505
申请日：2001-04-24
申请人： Brian W. Curran , Lisa Bryant Lacey , Gregory A. Northrop , Ruchir Puri , Leon Stok
发明人： Brian W. Curran , Lisa Bryant Lacey , Gregory A. Northrop , Ruchir Puri , Leon Stok
IPC分类号： G06F17/50 , H01L21/82 , H03K19/096 , H03K19/20
CPC分类号： G06F17/505
摘要： A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.
摘要翻译：高性能门库增加了锥形门。改变堆叠器件的宽度以减少通过一些输入引脚的延迟。例如在锥形NAND门中，NFET堆叠中的底部器件具有比顶部器件更宽的宽度，以牺牲较大的底部输入到输出引脚延迟为代价来实现较小的顶部输入以输出引脚延迟。使用合成算法的方法将输入网络修改为栅极引脚连接，并与锥形栅极交换传统的非锥形栅极，以改善时序关键路径的延迟。最新到达的门输入网络被互换，网络连接到顶针。然后将栅极转换成锥形栅极，提供通过底栅输入（不是时序关键）的路径。

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