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1. 发明授权

US5479640A Memory access system including a memory controller with memory redrive circuitry 失效
标题翻译：存储器存取系统包括具有存储器重新驱动电路的存储器控制器
公开(公告)号：US5479640A
公开(公告)日：1995-12-26
申请号：US85215
申请日：1993-06-30
申请人： Frank P. Cartman , Brian W. Curran , Matthew A. Krygowski , Tin-Chee Lo , Sandy N. Luu , Sanjay B. Patel , William W. Shen
发明人： Frank P. Cartman , Brian W. Curran , Matthew A. Krygowski , Tin-Chee Lo , Sandy N. Luu , Sanjay B. Patel , William W. Shen
IPC分类号： G06F12/02 , G11C8/00 , G11C11/408
CPC分类号： G06F12/0215 , G11C11/408 , G11C8/00
摘要： A memory access system for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. To improve memory access, both the memory controller and the main memory hardware remember the row address of the last access. Macro operation commands for fetch and store contain the last row address. The main memory hardware redrives that row address to the DRAMs after completion of an access, so that the memory controller need not provide a row address to the memory for each command of a command sequence.
摘要翻译：一种用于在寻址动态随机存取模块（DRAM）时改善存储器访问的存储器访问系统。存储器存取系统包括主存储器和存储器控制器。为了改善内存访问，内存控制器和主内存硬件都记住上次访问的行地址。用于获取和存储的宏操作命令包含最后一行地址。完成访问后，主存储器硬件将该行地址重新发送到DRAM，使得存储器控制器不需要为命令序列的每个命令向存储器提供行地址。

2. 发明授权

US5805789A Programmable computer system element with built-in self test method and apparatus for repair during power-on 失效
标题翻译：可编程计算机系统元件，具有内置自检方法和上电修理装置
公开(公告)号：US5805789A
公开(公告)日：1998-09-08
申请号：US846746
申请日：1997-04-03
申请人： William Vincent Huott , Tin-Chee Lo , Pradip Patel , Timothy John Slegel
发明人： William Vincent Huott , Tin-Chee Lo , Pradip Patel , Timothy John Slegel
IPC分类号： G06F11/22 , G06F11/27 , G06F11/273 , G11C29/00 , G11C29/32 , G11C29/44 , G06F11/00
CPC分类号： G11C29/789 , G06F11/2294 , G11C29/16 , G11C29/44 , G06F11/22 , G06F11/2205 , G06F11/27 , G11C2029/0407 , G11C29/32
摘要： Computer system element has a VLSI array with redundant areas and an ABIST (Array Built-In Self Test) system having mirror image fuse registers enabling scan of failed addresses to be used to replace hardware errors detected during power-on at a customer location. The ABIST controller allows self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy and useful for enabling array self-tests to be performed in a customer's office at power-on reset.
摘要翻译：计算机系统元件具有冗余区域的VLSI阵列和具有镜像熔丝寄存器的ABIST（阵列内置自检）系统，其能够扫描失败的地址，以替代在客户位置上电时检测到的硬件错误。 ABIST控制器允许修改测试功能（例如测试模式，读/写访问和测试序列），而不会对测试逻辑进行硬件更改。测试顺序由逻辑测试向量控制，可以改变，使开发复杂测试序列的任务相对容易和有用，可以在上电复位时在客户办公室中进行阵列自检。

3. 发明授权

US5822338A ECC-compare path of cache directory logic improvements 失效
标题翻译： ECC比较缓存目录逻辑改进路径
公开(公告)号：US5822338A
公开(公告)日：1998-10-13
申请号：US14503
申请日：1998-01-28
申请人： Tin-Chee Lo
发明人： Tin-Chee Lo
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/1064
摘要： Directory compare and ECC logic which is interfaced with the array's static and dynamic outputs for the ECC-compare path of a cache directory, using a three-output array providing a static output and a pair of complementary dynamic outputs. The static output is useed by the compare logic for a directory compare. The pair of complementary dynamic outputs provide dynamic signals (t and f) to drive the ECC logic only as ECC logic complementary signals which are coupled to drive a DCVS (Dynamic Cascode Voltage Switch) syndrome generator circuit. The static output signal performs compare-then-correct processing. The dynamic signals of each bit emanating from array are ECC checked but the static signal is not. The static signal is consistent with the t dynamic signal.
摘要翻译：目录比较和ECC逻辑，其与阵列的静态和动态输出接口，用于缓存目录的ECC比较路径，使用提供静态输出的三输出阵列和一对互补的动态输出。静态输出由目录比较的比较逻辑使用。这对互补动态输出提供动态信号（t和f），以驱动ECC逻辑，仅作为耦合到驱动DCVS（动态串联电压开关）校正子发生器电路的ECC逻辑互补信号。静态输出信号执行比较然后正确的处理。从阵列发出的每个位的动态信号被检查，但是静态信号不是。静态信号与t动态信号一致。

4. 发明授权

US5138705A Chip organization for an extendable memory structure providing busless internal page transfers 失效
标题翻译：可扩展内存结构的芯片组织提供无内部页面传输
公开(公告)号：US5138705A
公开(公告)日：1992-08-11
申请号：US371957
申请日：1989-06-26
申请人： Tin-Chee Lo , Arnold Weinberger
发明人： Tin-Chee Lo , Arnold Weinberger
IPC分类号： G06F12/06 , G06F12/02 , G06F12/08 , G11C8/12
CPC分类号： G11C8/12 , G06F12/08
摘要： A memory structure is described as comprised of a large number of fixed-size page frames. Each page frame in the memory is spread among all chips in the memory. The size of the memory structure may be extended or expanded by adding the same type of high-capacity chip originally used to construct the memory. (The chips may be constructed of semiconductor DRAM technology.) When the memory is extended/expanded, the fixed-size page frames have their lateral dimension decreased and their length increased, in accordance with the increase in the number of chips in the memory. A shift register on each chip accommodates the moving of pages within the memory structure as the page-frame shape and the redistribution of the page frame locations in the memory are changed when the number of chips in the memory structure is changed, without requiring any change in the internal structure of the chips. A page of data can be moved in two dimensions between any page frames within the memory structure without using any external bus, even though the size of the memory structure is changed. No bit in a page is moved off of its chip during a page move operation. All bits in a page are accessed and moved logically in parallel. Extremely fast page transfer rates are obtainable by the busless page move operations. Special addressing is provided that accommodates both the internal page move operations and data unit accesses in the memory structure for an external memory bus. Multiple logical memories can be accommodated in the memory structure.

5. 发明授权

US07596734B2 On-Chip AC self-test controller 有权
标题翻译：片上AC自检控制器
公开(公告)号：US07596734B2
公开(公告)日：2009-09-29
申请号：US12185172
申请日：2008-08-04
申请人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
发明人： John D. Flanagan , Jay R. Herring , Tin-Chee Lo
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/2891 , G01R31/31922
摘要： A system for performing AC self-test on an integrated circuit that includes a system clock for normal operation is provided. The system includes the system clock, self-test circuitry, a first and second test register to capture and launch test data in response to a sequence of data pulses, and a logic circuit to be tested. The self-test circuitry includes an AC self-test controller and a clock splitter. The clock splitter generates the sequence of data pulses including a long data capture pulse followed by an at speed data launch pulse and an at speed data capture pulse followed by a long data launch pulse. The at speed data launch pulse and the at speed data capture pulse are generated for a common cycle of the system clock.
摘要翻译：提供了一种用于在包括用于正常操作的系统时钟的集成电路上执行AC自检的系统。该系统包括系统时钟，自检电路，第一和第二测试寄存器，用于响应于数据脉冲序列捕获和发射测试数据，以及待测试的逻辑电路。自检电路包括一个交流自检控制器和时钟分离器。时钟分配器产生数据脉冲序列，包括长数据捕获脉冲，随后是速度数据发射脉冲和速度数据捕获脉冲，随后是长数据发射脉冲。为系统时钟的公共周期产生速度数据发射脉冲和速度数据捕获脉冲。

6. 发明申请

US20070240021A1 METHOD, SYSTEM AND PROGRAM PRODUCT FOR AUTONOMOUS ERROR RECOVERY FOR MEMORY DEVICES 失效
标题翻译：用于存储器件自动错误恢复的方法，系统和程序产品
公开(公告)号：US20070240021A1
公开(公告)日：2007-10-11
申请号：US11763653
申请日：2007-06-15
申请人： Sandeep Brahmadathan , Tin-Chee Lo , Jeffrey Turner
发明人： Sandeep Brahmadathan , Tin-Chee Lo , Jeffrey Turner
IPC分类号： G01R31/28
CPC分类号： G06F11/1032 , G06F12/0802
摘要： An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.
摘要翻译：为计算系统的存储器件提供自主的错误恢复方法。响应于对数据的请求，测试存储器设备的寻址数据和相关控制信息的错误。如果检测到错误，则响应于该请求，自动地检索并提供第二存储设备的寻址存储隔间的内容。作为示例，存储器设备可以是高速缓存，并且第二存储器设备可以是计算系统的主存储器。

7. 发明申请

US20060242509A1 Method and system for an on-chip AC self-test controller 有权
公开(公告)号：US20060242509A1
公开(公告)日：2006-10-26
申请号：US11323449
申请日：2005-12-30
申请人： John Flanagan , Jay Herring , Tin-Chee Lo
发明人： John Flanagan , Jay Herring , Tin-Chee Lo
IPC分类号： G01R31/28
CPC分类号： G01R31/31724 , G01R31/2891 , G01R31/31922
摘要： An exemplary embodiment of the present invention is a method for performing AC self-test on an integrated circuit that includes a system clock for use during normal operation. The method comprises applying a long data capture pulse to a first test register in response to said system clock. An at speed data launch pulse is applied to the first test register in response to said system clock. The data from the first register is input to a logic path in response to applying the at speed data launch pulse to the first test register. An at speed data capture pulse is applied to a second test register in response to the system clock. The output from the logic path is input to the second test register in response to applying the at speed data capture pulse to the second test register. A long data launch pulse is applied to the second test register in response to the system clock. An additional embodiment includes a system for performing AC self-test on an integrated circuit that includes a system clock.

8. 发明授权

US5359722A Method for shortening memory fetch time relative to memory store time and controlling recovery in a DRAM 失效
标题翻译：相对于存储器存储时间缩短存储器获取时间并控制DRAM中的恢复的方法
公开(公告)号：US5359722A
公开(公告)日：1994-10-25
申请号：US555960
申请日：1990-07-23
申请人： Shiu K. Chan , Joseph H. Datres, Jr. , Tin-Chee Lo
发明人： Shiu K. Chan , Joseph H. Datres, Jr. , Tin-Chee Lo
IPC分类号： G06F12/06 , G06F12/08 , G11C7/22 , G11C11/401 , G11C11/4076 , G11C29/00 , G11C29/42 , G06F12/00 , G06F1/04
CPC分类号： G11C7/22 , G11C11/4076
摘要： A method for reducing fetch time in a computer system provides a memory fetch cycle that is shorter than the memory store cycle. Each chip of the computer system has at least one dynamic random access memory array (DRAM) and a small high speed cache static random access memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and recovery in the DRAM. The RAS starts DRAM recovery for a fetch cycle at or near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that control DRAM recovery while fetching during DRAM data from the SRAMs, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.
摘要翻译：用于减少计算机系统中的获取时间的方法提供比存储器存储周期短的存储器获取周期。计算机系统的每个芯片在芯片上具有至少一个动态随机存取存储器阵列（DRAM）和小型高速缓存静态随机存取存储器（SRAM）。系统存储器控制器在生成DRAM子地址定时信号（RAS）和高速缓存地址定时信号（CAS）时识别存储器请求的获取或存储状态，用于实现SRAM中的位的访问和寻址以及在SRAM中的恢复 DRAM。在从芯片上的SRAM提取数据开始或接近开始的时候，RAS启动DRAM恢复，但是控制RAS在存储周期之前不开始DRAM恢复，直到完成SRAM数据存储。芯片上的时钟包含控制DRAM恢复的电路，在DRAM的DRAM数据期间提取DRAM，但是防止DRAM恢复开始直到SRAM中的数据存储完成。

9. 发明授权

US5058115A Fault tolerant computer memory systems and components employing dual level error correction and detection with lock-up feature 失效
标题翻译：故障容错计算机存储系统和组件采用双层错误校正和锁定功能检测
公开(公告)号：US5058115A
公开(公告)日：1991-10-15
申请号：US322255
申请日：1989-03-10
申请人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter , Tin-Chee Lo
发明人： Robert M. Blake , Douglas C. Bossen , Chin-Long Chen , John A. Fifield , Howard L. Kalter , Tin-Chee Lo
IPC分类号： G06F12/16 , G06F11/10
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

10. 发明授权

US07739557B2 Method, system and program product for autonomous error recovery for memory devices 失效
标题翻译：用于存储设备自主性错误恢复的方法，系统和程序产品
公开(公告)号：US07739557B2
公开(公告)日：2010-06-15
申请号：US11763653
申请日：2007-06-15
申请人： Sandeep Brahmadathan , Tin-Chee Lo , Jeffrey M. Turner
发明人： Sandeep Brahmadathan , Tin-Chee Lo , Jeffrey M. Turner
IPC分类号： G06K5/04 , G11C29/00 , G06F11/00
CPC分类号： G06F11/1032 , G06F12/0802
摘要： An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addressed storage compartment of a second memory device are automatically retrieved and provided responsive to the request. As an example, the memory device may be a cache and the second memory device may be main memory for the computing system.
摘要翻译：为计算系统的存储器件提供自主的错误恢复方法。响应于对数据的请求，测试存储器设备的寻址数据和相关控制信息的错误。如果检测到错误，则响应于该请求，自动地检索并提供第二存储设备的寻址存储隔间的内容。作为示例，存储器设备可以是高速缓存，并且第二存储器设备可以是计算系统的主存储器。

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