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1. 发明申请

US20110241423A1 Circuits, Systems and Methods to Detect and Accommodate Power Supply Voltage Droop 有权
标题翻译：检测和调节电源电压的电路，系统和方法Droop
公开(公告)号：US20110241423A1
公开(公告)日：2011-10-06
申请号：US12752515
申请日：2010-04-01
申请人： Jeffrey Todd Bridges , Sanjay B. Patel
发明人： Jeffrey Todd Bridges , Sanjay B. Patel
IPC分类号： H02J1/00
CPC分类号： G06F1/305 , Y10T307/406
摘要： Circuits, systems, and methods for monitoring a power supply voltage and determining if the power supply voltage has drooped are disclosed. In one embodiment, a voltage monitoring circuit is provided and configured to determine if the power supply voltage supplied to a functional circuit has drooped. When no droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a first mode. When droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a second mode. In this manner, operating margin in the power supply may be reduced since the functional circuit may be configured to properly operate when a voltage droop of the power supply voltage occurs.
摘要翻译：公开了用于监测电源电压并确定电源电压是否下降的电路，系统和方法。在一个实施例中，电压监视电路被提供并且被配置为确定提供给功能电路的电源电压是否下垂。当没有检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第一模式下操作的指示。当检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第二模式中操作的指示。以这种方式，由于功能电路可以被配置为在发生电源电压的电压下降时适当地操作，所以可以减少电源中的操作裕度。

2. 发明授权

US5479640A Memory access system including a memory controller with memory redrive circuitry 失效
标题翻译：存储器存取系统包括具有存储器重新驱动电路的存储器控制器
公开(公告)号：US5479640A
公开(公告)日：1995-12-26
申请号：US85215
申请日：1993-06-30
申请人： Frank P. Cartman , Brian W. Curran , Matthew A. Krygowski , Tin-Chee Lo , Sandy N. Luu , Sanjay B. Patel , William W. Shen
发明人： Frank P. Cartman , Brian W. Curran , Matthew A. Krygowski , Tin-Chee Lo , Sandy N. Luu , Sanjay B. Patel , William W. Shen
IPC分类号： G06F12/02 , G11C8/00 , G11C11/408
CPC分类号： G06F12/0215 , G11C11/408 , G11C8/00
摘要： A memory access system for improving memory access when addressing dynamic random access modules (DRAMs). The memory access system includes a main memory and a memory controller. To improve memory access, both the memory controller and the main memory hardware remember the row address of the last access. Macro operation commands for fetch and store contain the last row address. The main memory hardware redrives that row address to the DRAMs after completion of an access, so that the memory controller need not provide a row address to the memory for each command of a command sequence.
摘要翻译：一种用于在寻址动态随机存取模块（DRAM）时改善存储器访问的存储器访问系统。存储器存取系统包括主存储器和存储器控制器。为了改善内存访问，内存控制器和主内存硬件都记住上次访问的行地址。用于获取和存储的宏操作命令包含最后一行地址。完成访问后，主存储器硬件将该行地址重新发送到DRAM，使得存储器控制器不需要为命令序列的每个命令向存储器提供行地址。

3. 发明授权

US07447956B2 Method and apparatus for testing data steering logic for data storage having independently addressable subunits 有权
标题翻译：用于测试具有独立可寻址子单元的数据存储的数据转向逻辑的方法和装置
公开(公告)号：US07447956B2
公开(公告)日：2008-11-04
申请号：US11367959
申请日：2006-03-03
申请人： Lakshmikant Mamileti , Anand Krishnamurthy , Clint Wayne Mumford , Sanjay B Patel
发明人： Lakshmikant Mamileti , Anand Krishnamurthy , Clint Wayne Mumford , Sanjay B Patel
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/022 , G11C29/1201 , G11C29/44 , G11C29/4401 , G11C2029/1208
摘要： Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.
摘要翻译：通过为存储器阵列存储位置的每个可寻址子单元提供数据总线通道来测试存储器阵列的I / O中的读写数据转向逻辑。每个总线通道连接到比较器的数据输入。 BIST控制器通过写入指导逻辑将测试模式写入存储器，并并行读取测试模式以测试写入转向逻辑。 BIST控制器将测试模式并行地写入存储器，并通过读取转向逻辑读取测试模式，以测试读取转向逻辑。在这两种情况下，专用于每个总线通道的单独的比较器验证子数据在数据总线通道和存储器存储位置子单元之间正确移位。比较器在正常操作期间被有效地禁用，以防止逻辑门切换。

4. 发明授权

US07730282B2 Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture using a multi-bit age vector 失效
标题翻译：使用多位年龄向量在微处理器流水线架构中避免数据依赖性危害的方法和装置
公开(公告)号：US07730282B2
公开(公告)日：2010-06-01
申请号：US10916188
申请日：2004-08-11
申请人： James N. Dieffenderfer , Nathan S. Nunamaker , Sanjay B. Patel
发明人： James N. Dieffenderfer , Nathan S. Nunamaker , Sanjay B. Patel
IPC分类号： G06F9/00
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3826 , G06F9/3838 , G06F9/3855
摘要： A method and system for avoiding various hazards for instructions which are propagating through a microprocessor pipeline. When a plurality of instructions exist within the pipeline which read and write the same value, a vector is established to distinguish the older from the newer instructions. Further, before instructions are dispatched for execution, pointers are generated which identify the particular instruction which had the operand or parameter value needed. Accordingly, by monitoring both the recent vector and pointers, dated dependency hazards can be avoided.
摘要翻译：一种用于避免通过微处理器管道传播的指令的各种危险的方法和系统。当流水线内存在多个读取和写入相同值的指令时，建立一个向量来区分较旧的指令。此外，在分派指令执行之前，生成指针，该指针标识具有操作数或参数值所需的特定指令。因此，通过监视最近的向量和指针，可以避免日期依赖危害。

5. 发明授权

US09483098B2 Circuits, systems and methods to detect and accommodate power supply voltage droop 有权
标题翻译：检测电源电压下降的电路，系统和方法
公开(公告)号：US09483098B2
公开(公告)日：2016-11-01
申请号：US12752515
申请日：2010-04-01
申请人： Jeffrey Todd Bridges , Sanjay B. Patel
发明人： Jeffrey Todd Bridges , Sanjay B. Patel
IPC分类号： H02J3/14 , G06F1/30
CPC分类号： G06F1/305 , Y10T307/406
摘要： Circuits, systems, and methods for monitoring a power supply voltage and determining if the power supply voltage has drooped are disclosed. In one embodiment, a voltage monitoring circuit is provided and configured to determine if the power supply voltage supplied to a functional circuit has drooped. When no droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a first mode. When droop of the power supply voltage is detected, the voltage monitoring circuit is configured to provide an indication to the functional circuit to operate in a second mode. In this manner, operating margin in the power supply may be reduced since the functional circuit may be configured to properly operate when a voltage droop of the power supply voltage occurs.
摘要翻译：公开了用于监测电源电压并确定电源电压是否下降的电路，系统和方法。在一个实施例中，电压监视电路被提供并且被配置为确定提供给功能电路的电源电压是否下垂。当没有检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第一模式下操作的指示。当检测到电源电压下降时，电压监视电路被配置为向功能电路提供在第二模式中操作的指示。以这种方式，由于功能电路可以被配置为在发生电源电压的电压下降时适当地操作，所以可以减少电源中的操作裕度。

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