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1. 发明授权

US09501407B1 First-in-first-out memory with dual memory banks 有权
标题翻译：先进先出的双存储器存储器
公开(公告)号：US09501407B1
公开(公告)日：2016-11-22
申请号：US13235228
申请日：2011-09-16
申请人： Ray Ruey-Hsien Hu , Andy L. Lee , David Lewis , Tony Ngai , Haiming Yu , Hao-Yuan Howard Chou
发明人： Ray Ruey-Hsien Hu , Andy L. Lee , David Lewis , Tony Ngai , Haiming Yu , Hao-Yuan Howard Chou
IPC分类号： G06F12/06 , G06F13/16
CPC分类号： G06F12/0607 , G06F13/1689 , Y02D10/14
摘要： A first-in-first-out memory may have first and second memory banks. A write controller may write data into the first and second memory banks. In performing write operations, the write controller may determine whether to write the data into the first bank or the second bank by evaluating a first bank empty flag and a second bank empty flag. When transitioning between writing in the first bank and the second bank, the write controller may latch a write address value indicative of the last location at which valid data was written in a given bank. A read controller may read data from the first and second memory bank. The read controller may determine when to transition between reading in the first bank and reading in the second bank by comparing a current read address to the latched write address value.
摘要翻译：先入先出的存储器可以具有第一和第二存储体。写控制器可以将数据写入第一和第二存储体。在执行写入操作时，写入控制器可以通过评估第一存储体空标志和第二存储体空标志来确定是否将数据写入第一存储体或第二存储体。当在第一组和第二组中的写入之间转换时，写入控制器可以锁存指示在给定存储体中写入有效数据的最后位置的写入地址值。读取控制器可以从第一和第二存储体读取数据。读取控制器可以通过将当前读取地址与锁存的写入地址值进行比较来确定何时在第一存储区中的读取和第二存储区中的读取之间转换。

2. 发明授权

US06593772B2 Embedded memory blocks for programmable logic 有权
公开(公告)号：US06593772B2
公开(公告)日：2003-07-15
申请号：US10177785
申请日：2002-06-19
申请人： Tony Ngai , Sergey Shumarayev , Wei-Jen Huang , Rakesh Patel , Tin Lai
发明人： Tony Ngai , Sergey Shumarayev , Wei-Jen Huang , Rakesh Patel , Tin Lai
IPC分类号： H03K19177
CPC分类号： G11C5/025 , H03K19/17736 , H03K19/1776
摘要： A high-performance programmable logic architecture has embedded memory (608). arranged at the peripheries or edges of the integrated circuit. This enhances the performance of the programmable logic integrated circuit by shortening the lengths of the programmable interconnect (748). In a specific embodiment, the memory blocks (703) are organized in rows along the top and bottom edges of the integrated circuit. The logic elements (805) can be directly programmable routed and connected to driver blocks (809) of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources (815, 825). Using similar direct programmable interconnections (828, 830, 835), the logic blocks can directly programmable connect to the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.

3. 发明授权

US06556502B2 Memory circuitry for programmable logic integrated circuit devices 有权
公开(公告)号：US06556502B2
公开(公告)日：2003-04-29
申请号：US10134886
申请日：2002-04-26
申请人： Tony Ngai , Nitin Prasad , Thungoc Tran
发明人： Tony Ngai , Nitin Prasad , Thungoc Tran
IPC分类号： G11C800
CPC分类号： H03K19/1776 , G11C7/1075 , G11C8/16 , G11C11/005
摘要： A programmable logic device includes, in addition to the usual regions of programmable logic and the programmable interconnect, at least one region of memory which has multiple independently usable write and/or read ports (e.g., two write ports and two read ports). Every memory cell in the memory region is accessible from any of these ports. This enables the memory region to be used to provide either one relatively large memory or two somewhat smaller memories, each occupying a fraction of the full memory. In the latter case, the two memories provided can have any of many different sizes relative to one another. Many different modes or combinations of modes of operating the memory region or parts of the memory region are possible.

4. 发明授权

US06407576B1 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连和输入/输出资源
公开(公告)号：US06407576B1
公开(公告)日：2002-06-18
申请号：US09516921
申请日：2000-03-02
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： H01L2500
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

5. 发明授权

US06239615B1 High-performance interconnect 有权
标题翻译：高性能互连
公开(公告)号：US06239615B1
公开(公告)日：2001-05-29
申请号：US09235371
申请日：1999-01-20
申请人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
发明人： Tony Ngai , Sergey Shumarayev , Sammy Cheung , Rakesh Patel , Vinson Chan
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H01L23/5222 , H01L2924/0002 , H03K19/1778 , H03K19/17792 , H03K19/17796 , H01L2924/00
摘要： Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g., 405, 720) so the parasitic coupling capacitances (e.g., 425) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.
摘要翻译：为集成电路提供高性能互连的技术将提高整体集成电路性能。这些技术包括布置，布置和制造信号导体（例如，405,720），使得寄生耦合电容（例如425）最小化并且寄生电阻降低。这些技术将最小化导体之间串扰噪声的影响，从而提高整体集成电路性能。

6. 发明授权

US08760328B1 Interface circuitry for an integrated circuit system 有权
标题翻译：集成电路系统的接口电路
公开(公告)号：US08760328B1
公开(公告)日：2014-06-24
申请号：US13620126
申请日：2012-09-14
申请人： Wei Yee Koay , Chin Ghee Ch'ng , Ket Chiew Sia , Tony Ngai , Sean Woei Voon
发明人： Wei Yee Koay , Chin Ghee Ch'ng , Ket Chiew Sia , Tony Ngai , Sean Woei Voon
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： An integrated circuit system may include a first integrated circuit (IC), a second IC, and interface circuitry. The first IC is operable to output a parallel data stream at a first data rate. The second IC is operable to output a serialized data stream at a second date rate. The second data rate may be different than the first data rate. The interface circuitry may be coupled between the first integrated circuit and the second integrated circuit. The interface circuitry may be operable to convert the parallel data stream received from the first IC into a serialized data stream with the second data rate. The interface circuitry may be also operable to convert the serialized data stream received from the second IC to a parallel data stream with the first data rate.
摘要翻译：集成电路系统可以包括第一集成电路（IC），第二IC和接口电路。第一IC可操作以以第一数据速率输出并行数据流。第二IC可操作地以第二日期速率输出串行数据流。第二数据速率可能不同于第一数据速率。接口电路可以耦合在第一集成电路和第二集成电路之间。接口电路可以用于将从第一IC接收的并行数据流转换成具有第二数据速率的串行数据流。接口电路还可以用于将从第二IC接收的串行数据流转换成具有第一数据速率的并行数据流。

7. 发明授权

US06989689B2 Interconnection and input/output resources for programmable logic integrated circuit devices 失效
公开(公告)号：US06989689B2
公开(公告)日：2006-01-24
申请号：US10852858
申请日：2004-05-24
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

8. 发明授权

US06894533B2 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连和输入/输出资源
公开(公告)号：US06894533B2
公开(公告)日：2005-05-17
申请号：US10458431
申请日：2003-06-09
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： G06F7/50 , G06F7/506 , H03K19/173 , H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

9. 发明授权

US06366120B1 Interconnection resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连资源
公开(公告)号：US06366120B1
公开(公告)日：2002-04-02
申请号：US09517146
申请日：2000-03-02
申请人： James Schleicher , James Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
发明人： James Schleicher , James Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
IPC分类号： H03K190177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17792
摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.
摘要翻译：可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

10. 发明授权

US6154059A High performance output buffer 有权
标题翻译：高性能输出缓冲器
公开(公告)号：US6154059A
公开(公告)日：2000-11-28
申请号：US199705
申请日：1998-11-24
申请人： Sammy Cheung , John Lam , Rakesh Patel , Tony Ngai
发明人： Sammy Cheung , John Lam , Rakesh Patel , Tony Ngai
IPC分类号： H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00361
摘要： An output buffer has internal circuitry connected between an input node and an output node. The internal circuitry includes a quiet voltage supply connected to a first set of transistors of the internal circuitry and a noisy voltage supply connected to a second set of transistors of the internal circuitry. The noisy voltage supply is at a voltage level higher than the quiet voltage supply. The first set of transistors and the second set of transistors provide isolation between the noisy voltage supply and the quiet voltage supply. The first set of transistors and the second set of transistors also provide complete digital high and low internal signal levels by using at least one transistor operative to supplement the complete shut-off and turn-on of transistors of the first set of transistors and the second set of transistors. The output buffer also features a ground bounce circuit, a slew rate control circuit, a transition accelerator circuit, a Personal Computer Interface (PCI) compatibility circuit, and a PCI control circuit.
摘要翻译：输出缓冲器具有连接在输入节点和输出节点之间的内部电路。内部电路包括连接到内部电路的第一组晶体管的静音电压源和连接到内部电路的第二组晶体管的噪声电压源。嘈杂的电源电压处于高于静态电源的电压电平。第一组晶体管和第二组晶体管提供噪声电压源和安静电源之间的隔离。第一组晶体管和第二组晶体管还通过使用至少一个晶体管提供完整的数字高和低内部信号电平，该晶体管可操作地补充第一组晶体管的晶体管的完全截止和导通，第二组晶体管的第二组一组晶体管。输出缓冲器还具有接地反弹电路，压摆率控制电路，转换加速器电路，个人计算机接口（PCI）兼容性电路和PCI控制电路。

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