专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5875130A Method for programming flash electrically erasable programmable read-only memory 失效
标题翻译：闪存电可擦除可编程只读存储器的编程方法
公开(公告)号：US5875130A
公开(公告)日：1999-02-23
申请号：US085705
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chan , Colin S. Bill
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chan , Colin S. Bill
IPC分类号： G11C16/10 , G11C16/34 , G11C13/00
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/3404
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse. The bias voltage is preferably applied during both the overerase correction and programming pulses, reducing the power requirements and reducing the background leakage of the cells to a level at which program, read and overerase correction operations can be operatively performed.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括半导体衬底和多个场效应晶体管存储单元，每个具有形成在衬底上的源极，漏极，浮置栅极和控制栅极。控制器控制电源以将操作脉冲施加到单元的漏极，并且在施加操作脉冲时将源施加到单元的衬底偏置电压，所述偏置电压具有被选择为减少或基本上消除的值电池中的漏电流。操作脉冲可以是过高修正脉冲。在这种情况下，在过扫描校正脉冲的持续时间内，向控制栅极施加基本上等于偏置电压的电压。操作脉冲也可以是编程脉冲。在这种情况下，在编程脉冲的持续时间内，将高于偏置电压的电压施加到所选字线的控制栅极。偏置电压优选地在过电压过程校正和编程脉冲期间都被施加，从而降低功率需求并将电池的背景泄漏减小到能够可操作地执行程序，读取和过电压校正操作的电平。

2. 发明授权

US06452840B1 Feedback method to optimize electric field during channel erase of flash memory devices 有权
标题翻译：用于优化闪存器件通道擦除期间电场的反馈方法
公开(公告)号：US06452840B1
公开(公告)日：2002-09-17
申请号：US09693649
申请日：2000-10-21
申请人： Ravi S. Sunkavalli , Lee Cleveland , Sameer S. Haddad , Richard Fastow , Tim Thurgate
发明人： Ravi S. Sunkavalli , Lee Cleveland , Sameer S. Haddad , Richard Fastow , Tim Thurgate
IPC分类号： G11C1604
CPC分类号： G11C16/3477 , G11C16/344 , G11C16/3445 , G11C16/3472
摘要： A method of erasing a flash memory device that improves reliability and reduces the decrease in erase speed. The state of erasure is determined either during an erase phase or a verify phase and the information is fedback to a controller that adjusts the erase vertical electrical field that is to be applied to the array. The vertical electrical field is adjusted by changing the gate voltage, the well voltage or changing both simultaneously.
摘要翻译：一种擦除闪速存储器件的方法，其提高可靠性并减少擦除速度的降低。在擦除阶段或验证阶段期间确定擦除状态，并将信息反馈到调整要应用于阵列的擦除垂直电场的控制器。通过改变栅极电压，井电压或同时改变两者来调节垂直电场。

3. 发明授权

US5901090A Method for erasing flash electrically erasable programmable read-only memory (EEPROM) 失效
标题翻译：擦除闪存电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US5901090A
公开(公告)日：1999-05-04
申请号：US85552
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Colin S. Bill , Vei-Han Chen
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Colin S. Bill , Vei-Han Chen
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/3409 , G11C16/16
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, and a power source for supplying a plurality of voltages to the cells. A controller controls the power source to apply at least one erase pulse to the cells. Then, at least one overerase correction or "soft programming" pulse is applied to the cells during which the source, drain and control gate voltages of the cells are such that the threshold voltages of overerased cells will be increased, but least erased cells will not be disturbed. The overerase correction pulses thereby tighten the threshold voltage distribution. A source to substrate bias voltage is applied for the duration of the overerase correction pulses which reduces the background leakage of the cells to a level at which the overerase correction operation can be effectively performed, even in applications with low supply voltages.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括多个具有源极，漏极，浮动栅极和控制栅极的场效应晶体管存储单元，以及用于向单元提供多个电压的电源。控制器控制电源向单元施加至少一个擦除脉冲。然后，将至少一个过度校正或“软编程”脉冲施加到单元，在该单元期间，单元的源极，漏极和控制栅极电压使得过度流过的单元的阈值电压将增加，但是最小擦除的单元将不会被打扰过度校正脉冲从而使阈值电压分布紧密。在过渡期校正脉冲的持续时间内施加衬底偏置电压源，即使在具有低电源电压的应用中，也可以将电池的背景泄漏降低到可以有效执行过电压修正操作的水平。

4. 发明授权

US06275415B1 Multiple byte channel hot electron programming using ramped gate and source bias voltage 有权
标题翻译：使用斜坡栅极和源偏置电压的多字节通道热电子编程
公开(公告)号：US06275415B1
公开(公告)日：2001-08-14
申请号：US09416563
申请日：1999-10-12
申请人： Sameer S. Haddad , Ravi S. Sunkavalli , Wing Han Leung , John Chen , Ravi Prakash Gutala , Colin Bill , Vei-Han Chan
发明人： Sameer S. Haddad , Ravi S. Sunkavalli , Wing Han Leung , John Chen , Ravi Prakash Gutala , Colin Bill , Vei-Han Chan
IPC分类号： G11C1604
CPC分类号： G11C16/12
摘要： A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated. In another embodiment, a bias voltage is applied to the common source terminal and a bias voltage is applied to the common well voltage. The combination of the voltages applied to the control gates and to the sources decreases loading on the bitlines to ensure that VDS does not fall below a required level necessary for the maintenance of the hot carrier effect during programming. A bias voltage can also be applied to the wells of the memory cells while the common source terminal is held at ground. Feedback control of the programming gate voltages can be used to control the power required for programming.
摘要翻译：一种具有多个存储单元的存储器件，每个存储体具有多个存储器单元，以及一种编程器件中的多个存储器单元的方法，其中偏置电压施加到多个存储器单元的公共源极端子，并且将时变电压施加到要编程的存储单元。在一个实施例中，施加到要编程的存储器单元的栅极的电压是斜坡电压。在第二实施例中，施加到待编程的存储器单元的栅极的电压是增加的阶梯电压。在另一个实施例中，选择施加到公共源极端子的偏置电压和施加到要编程的存储器单元的控制栅极的电压，使得流过被编程的单元的电流减小，并且来自存储器单元的泄漏电流不被编程的基本上被消除。在另一个实施例中，将偏置电压施加到公共源极端子，并将偏置电压施加到公共井电压。施加到控制栅极和源极的电压的组合减少了位线上的负载，以确保VDS不会降低到在编程期间维持热载流子效应所需的水平。偏置电压也可以施加到存储单元的阱，同时公共源极保持在地。编程栅极电压的反馈控制可用于控制编程所需的功率。

5. 发明授权

US06188609B1 Ramped or stepped gate channel erase for flash memory application 有权
标题翻译：用于闪存应用的斜坡或步进门控通道擦除
公开(公告)号：US06188609B1
公开(公告)日：2001-02-13
申请号：US09307259
申请日：1999-05-06
申请人： Ravi S. Sunkavalli , Sameer S. Haddad
发明人： Ravi S. Sunkavalli , Sameer S. Haddad
IPC分类号： G11C1606
CPC分类号： G11C16/16
摘要： A method for erasing a flash EEPROM cell by applying a voltage differential between the control gate and the well of the memory cell. The voltage differential can be a ramped or stepped voltage applied to the control gate, a ramped or stepped voltage applied to the well, or a ramped or stepped voltage applied to the control gate and a ramped or stepped voltage applied to the well. The ramped voltages can have a constant slope or the slope can vary. The stepped voltages can be incremented equally or unequally. The voltages applied to the well or to the control gate is ramped or stepped until a selected number of memory cells verify as erased at which time the voltages applied to the well or to the control gate is clamped until the erase procedure is finished.
摘要翻译：一种通过在控制栅极和存储单元的阱之间施加电压差来擦除快闪EEPROM单元的方法。电压差可以是施加到控制栅极的斜坡或阶梯电压，施加到阱的斜坡或阶梯电压，或施加到控制栅极的斜坡或阶梯电压以及施加到阱的斜坡或阶梯电压。斜坡电压可以具有恒定的斜率或斜率可以变化。阶梯电压可以相等或不平等地递增。施加到阱或控制栅极的电压是斜坡或阶梯直到选定数量的存储单元验证为擦除，此时施加到阱或控制栅极的电压被钳位直到擦除过程完成。

6. 发明授权

US6157572A Method for erasing flash electrically erasable programmable read-only memory (EEPROM) 失效
标题翻译：擦除闪存电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US6157572A
公开(公告)日：2000-12-05
申请号：US85680
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chen , Colin S. Bill
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chen , Colin S. Bill
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/16
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power supply for generating erase pulses. A controller controls the power supply to apply an erase pulse to all wordlines which are not deselected. Then, an erase verify procedure is applied to the cells in sequence. If all cells connected to a wordline pass the erase verify test, the wordline is deselected such that subsequent erase pulses will not be applied to the wordline and possibly cause the cells to become overerased. In one embodiment of the invention, erase verify is performed on all of the cells after an erase pulse is applied. The erase operation is completed when all cells pass erase verify. In another embodiment, erase verify is applied to each cell in sequence, with erase pulses being applied until each current cell passes erase verify. The wordlines can be deselected individually or in groups. The invention results in a tightening of the threshold voltage distribution of the cells.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括多个浮栅晶体管存储单元，连接到单元的多个字线和用于产生擦除脉冲的电源。控制器控制电源以将擦除脉冲施加到未被取消选择的所有字线。然后，按顺序对单元应用擦除验证程序。如果连接到字线的所有单元都通过擦除验证测试，则字线被取消选择，使得后续的擦除脉冲不会被施加到字线并且可能导致单元变得过高。在本发明的一个实施例中，在施加擦除脉冲之后对所有单元执行擦除验证。当所有单元通过擦除验证时，擦除操作完成。在另一实施例中，按顺序对每个单元施加擦除验证，其中施加擦除脉冲，直到每个当前单元通过擦除验证。字母可以单独或分组取消选择。本发明导致电池的阈值电压分布的紧缩。

7. 发明授权

US06974989B1 Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing 有权
标题翻译：用于保护记忆细胞免受后期处理中的紫外线辐射损伤和紫外线辐射诱导的充电的结构和方法
公开(公告)号：US06974989B1
公开(公告)日：2005-12-13
申请号：US10841933
申请日：2004-05-06
申请人： Cinti X. Chen , Boon-Yong Ang , Hajime Wada , Sameer S. Haddad , Inkuk Kang
发明人： Cinti X. Chen , Boon-Yong Ang , Hajime Wada , Sameer S. Haddad , Inkuk Kang
IPC分类号： H01L21/8246 , H01L21/8247 , H01L27/108 , H01L27/115
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The structure further comprises a first interlayer dielectric layer situated over the at least one memory cell and over the substrate. The structure further comprises an oxide cap layer situated on the first interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises an etch stop layer comprising TCS nitride situated on the oxide cap layer, where the etch stop layer blocks UV radiation. The structure further comprises a second interlayer dielectric layer situated on the etch stop layer. The structure may further comprise a trench situated in the second interlayer dielectric layer and the etch stop layer, where the trench is filled with copper. The structure may further comprise an anti-reflective coating layer situated on the second interlayer dielectric layer.
摘要翻译：根据一个示例性实施例，一种结构包括基底。该结构还包括位于基板上的至少一个存储单元。所述结构还包括位于所述至少一个存储单元上并位于所述衬底之上的第一层间介电层。该结构还包括位于第一层间介电层上的氧化物覆盖层。根据该示例性实施例，该结构还包括位于氧化物覆盖层上的包含TCS氮化物的蚀刻停止层，其中蚀刻停止层阻挡UV辐射。该结构还包括位于蚀刻停止层上的第二层间介电层。该结构还可以包括位于第二层间电介质层和蚀刻停止层中的沟槽，其中沟槽被铜填充。该结构还可以包括位于第二层间介电层上的抗反射涂层。

8. 发明授权

US06808996B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06808996B1
公开(公告)日：2004-10-26
申请号：US09376659
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

9. 发明授权

US06795357B1 Method for reading a non-volatile memory cell 失效
标题翻译：读取非易失性存储单元的方法
公开(公告)号：US06795357B1
公开(公告)日：2004-09-21
申请号：US10283590
申请日：2002-10-30
申请人： Zhizheng Liu , Yi He , Mark W. Randolph , Sameer S. Haddad
发明人： Zhizheng Liu , Yi He , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C700
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/26
摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a source voltage to a first bit line that is the source of the selected memory cell and applying a drain voltage to a second bit line that forms a drain junction with the channel region. The source voltage may be a small positive voltage and the drain voltage may be greater than the source voltage. A read voltage is applied to a selected one of the word lines that forms a gate over the charge storage region and a bias voltage is applied to non-selected word lines in the array. The bias voltage may be a negative voltage.
摘要翻译：检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括将源电压施加到作为所选存储单元的源的第一位线并施加到与沟道区形成漏极结的第二位线的漏极电压。源极电压可以是小的正电压，并且漏极电压可能大于源极电压。将读取电压施加到在电荷存储区域上形成栅极的所选择的一条字线，并且将偏置电压施加到阵列中的未选择的字线。偏置电压可以是负电压。

10. 发明授权

US06548334B1 Capping layer 失效
标题翻译：封盖层
公开(公告)号：US06548334B1
公开(公告)日：2003-04-15
申请号：US10179061
申请日：2002-06-24
申请人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
发明人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
IPC分类号： H01L21337
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： A method of fabricating an improved flash memory device having core stacks and periphery stacks which are protected with an oxide layer, a protective layer and an insulating layer. A high energy dopant implant is used to pass the dopant through the insulating layer, the protective layer and oxide layer into the substrate to create source and drain regions, without using a self aligned etch. The flash memory device has an intermetallic dielectric layer placed over the core stacks and the periphery stacks. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The use of a high energy dopant implant to pass through dopant through the insulating layer, the protective layer and the oxide layer into the substrate without the use of a self aligned source etch, reduces damage to the core stacks and periphery stacks caused by various etches during the production of the flash memory device and provides insulation to reduce unwanted current between the tungsten plug and the stacks.
摘要翻译：一种制造具有由氧化层，保护层和绝缘层保护的芯堆叠和外围堆叠的改进的闪存器件的方法。使用高能掺杂剂注入来使掺杂剂通过绝缘层，保护层和氧化物层进入衬底以产生源区和漏区，而不使用自对准蚀刻。闪存器件具有放置在芯堆叠和外围堆叠体上的金属间介电层。将钨塞放置在金属间介电层中以提供与闪存器件的漏极的电连接。使用高能掺杂剂注入物通过掺杂剂通过绝缘层，保护层和氧化物层进入衬底而不使用自对准源蚀刻，减少了由各种蚀刻引起的芯堆叠和外围堆叠的损坏在制造闪速存储器件期间提供绝缘以减少钨插头和堆叠之间的不必要的电流。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式