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1. 发明授权

US06803265B1 Liner for semiconductor memories and manufacturing method therefor 有权
标题翻译：半导体存储器用衬垫及其制造方法
公开(公告)号：US06803265B1
公开(公告)日：2004-10-12
申请号：US10109234
申请日：2002-03-27
申请人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn M. Hopper , Pei-Yuan Gao
发明人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn M. Hopper , Pei-Yuan Gao
IPC分类号： H01L21337
CPC分类号： H01L27/11568 , H01L23/26 , H01L27/115 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A manufacturing method for an integrated circuit memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, ultra-violet block data retention liner covers the wordline and the charge-trapping dielectric layer. The reduced hydrogen levels reduce the charge loss compared to prior art. The surface of the liner is processed to block UV light before completing the integrated circuit.
摘要翻译：集成电路存储器的制造方法包括提供半导体衬底和沉积电荷俘获电介质层。植入第一和第二位线，并存放字线层。硬掩模层沉积在字线层上。光刻胶沉积在字线层上并用于形成硬掩模。去除光致抗蚀剂。使用硬掩模处理字线层以形成字线，并且去除硬掩模。减少的氢，紫外阻挡数据保持衬里覆盖字线和电荷捕获介电层。与现有技术相比，降低的氢含量降低了电荷损失。在完成集成电路之前，衬里的表面被处理以阻挡UV光。

2. 发明授权

US07297592B1 Semiconductor memory with data retention liner 有权
标题翻译：具有数据保留衬垫的半导体存储器
公开(公告)号：US07297592B1
公开(公告)日：2007-11-20
申请号：US11195201
申请日：2005-08-01
申请人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn Hopper , Pei-Yuan Gao
发明人： Minh Van Ngo , Arvind Halliyal , Tazrien Kamal , Hidehiko Shiraiwa , Rinji Sugino , Dawn Hopper , Pei-Yuan Gao
IPC分类号： H01L21/8247
CPC分类号： H01L21/28282 , H01L21/3185 , H01L27/11568
摘要： A manufacturing method for a dual bit flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer with the depositing performed without using ammonia at an ultra-slow deposition rate. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, high-density data retention liner to reduce charge loss, covers the wordline and the charge-trapping dielectric layer. An interlayer dielectric layer is deposited over the data retention liner.
摘要翻译：一种用于双位闪速存储器的制造方法包括提供半导体衬底和沉积电荷捕获电介质层，其中沉积是以超低沉积速率使用氨而不使用氨。植入第一和第二位线，并存放字线层。硬掩模层沉积在字线层上。光刻胶沉积在字线层上并用于形成硬掩模。去除光致抗蚀剂。使用硬掩模处理字线层以形成字线，并且去除硬掩模。减少氢，高密度数据保持衬垫以减少电荷损失，覆盖字线和电荷捕获电介质层。层间绝缘层沉积在数据保持衬里上。

3. 发明授权

US06884681B1 Method of manufacturing a semiconductor memory with deuterated materials 有权
标题翻译：用氘代材料制造半导体存储器的方法
公开(公告)号：US06884681B1
公开(公告)日：2005-04-26
申请号：US10672093
申请日：2003-09-26
申请人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
发明人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
IPC分类号： H01L21/336 , H01L21/8246
CPC分类号： H01L27/11568 , H01L29/66833
摘要： A method for manufacturing a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.
摘要翻译：一种用于制造MirrorBit（闪存）闪存的方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。植入第一和第二位线，并在完成内存之前形成字线。在字线之间形成间隔，并且在字线之间形成层间电介质层。第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

4. 发明授权

US06670241B1 Semiconductor memory with deuterated materials 有权
标题翻译：具有氘化材料的半导体存储器
公开(公告)号：US06670241B1
公开(公告)日：2003-12-30
申请号：US10128771
申请日：2002-04-22
申请人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
发明人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L29/66833
摘要： A device and method for manufacturing thereof for a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.
摘要翻译：用于制造MirrorBit（闪存）闪存的器件及其制造方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。植入第一和第二位线，并在完成内存之前形成字线。在字线之间形成间隔，并且在字线之间形成层间电介质层。第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

5. 发明授权

US07074677B1 Memory with improved charge-trapping dielectric layer 有权
标题翻译：具有改进的电荷俘获介电层的存储器
公开(公告)号：US07074677B1
公开(公告)日：2006-07-11
申请号：US10307189
申请日：2002-11-29
申请人： Arvind Halliyal , Minh Van Ngo , Hidehiko Shiraiwa , Rinji Sugino
发明人： Arvind Halliyal , Minh Van Ngo , Hidehiko Shiraiwa , Rinji Sugino
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , Y10S438/954
摘要： A manufacturing method for a Flash memory includes depositing a first dielectric layer on a semiconductor substrate. A low hydrogen charge-trapping dielectric layer is deposited followed by a second dielectric layer. First and second bitlines are implanted and a wordline layer is deposited.
摘要翻译：一种闪速存储器的制造方法，包括在半导体衬底上沉积第一介电层。沉积低氢电荷捕获电介质层，然后沉积第二介电层。植入第一和第二位线，并存放字线层。

6. 发明授权

US07023046B2 Undoped oxide liner/BPSG for improved data retention 有权
标题翻译：未掺杂氧化物衬垫/ BPSG，以改善数据保留
公开(公告)号：US07023046B2
公开(公告)日：2006-04-04
申请号：US10617450
申请日：2003-07-11
申请人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
发明人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/31612 , H01L21/31625 , H01L27/115 , H01L29/511
摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.
摘要翻译：具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在相同的沉积室。

7. 发明授权

US07060554B2 PECVD silicon-rich oxide layer for reduced UV charging 有权
标题翻译： PECVD富氧氧化物层，用于减少紫外线充电
公开(公告)号：US07060554B2
公开(公告)日：2006-06-13
申请号：US10617451
申请日：2003-07-11
申请人： Minh Van Ngo , Mark Ramsbey , Tazrien Kamal , Pei Yuan Gao
发明人： Minh Van Ngo , Mark Ramsbey , Tazrien Kamal , Pei Yuan Gao
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/02164 , H01L21/02274 , H01L21/31604 , H01L21/76829 , H01L21/76834 , H01L23/552 , H01L27/115 , H01L29/66825 , H01L2924/0002 , H01L2924/00
摘要： A Si-rich silicon oxide layer having reduced UV transmission is deposited by PECVD, on an interlayer dielectric, prior to metallization, thereby reducing Vt. Embodiments include depositing a UV opaque Si-rich silicon oxide layer having an R.I. of 1.7 to 2.0.
摘要翻译：在金属化之前，通过PECVD在层间电介质上沉积具有减少的UV透射的富Si氧化硅层，从而减少V O。实施方案包括沉积具有1.7至2.0的R.I.的UV不透明的富Si氧化硅层。

8. 发明授权

US06653190B1 Flash memory with controlled wordline width 失效
标题翻译：具有受控字线宽度的闪存
公开(公告)号：US06653190B1
公开(公告)日：2003-11-25
申请号：US10023436
申请日：2001-12-15
申请人： Jean Y. Yang , Kouros Ghandehari , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Dawn M. Hopper , Angela T. Hui , Scott A. Bell
发明人： Jean Y. Yang , Kouros Ghandehari , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Dawn M. Hopper , Angela T. Hui , Scott A. Bell
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method of manufacturing for a MirrorBit® Flash memory includes depositing a charge-trapping material over a semiconductor substrate and implanting first and second bitlines in the semiconductor substrate. A wordline material is deposited over the charge-trapping dielectric material and a hard mask material deposited thereon. An anti-reflective coating (ARC) material is deposited on the hard mask material and a photoresist material is deposited on the ARC followed by processing the photoresist material and the ARC material to form a photomask of a patterned photoresist and a patterned ARC. The hard mask material is processed using the photomask to form a hard mask. The patterned photoresist is removed and then the patterned ARC without damaging the hard mask or the wordline material. The wordline material is processed using the hard mask to form a wordline and the hard mask is removed without damaging the wordline or the charge-trapping material.
摘要翻译：用于MirrorBit（闪存）闪存的制造方法包括在半导体衬底上沉积电荷捕获材料并在半导体衬底中注入第一和第二位线。字线材料沉积在电荷俘获电介质材料上并沉积在其上的硬掩模材料。将抗反射涂层（ARC）材料沉积在硬掩模材料上，并且将光致抗蚀剂材料沉积在ARC上，随后处理光致抗蚀剂材料和ARC材料以形成图案化光致抗蚀剂和图案化ARC的光掩模。使用光掩模处理硬掩模材料以形成硬掩模。去除图案化的光致抗蚀剂，然后去除图案化的ARC，而不损坏硬掩模或字线材料。使用硬掩模处理字线材料以形成字线，并且去除硬掩模而不损坏字线或电荷捕获材料。

9. 发明授权

US06617215B1 Memory wordline hard mask 有权
标题翻译：内存字线硬掩模
公开(公告)号：US06617215B1
公开(公告)日：2003-09-09
申请号：US10109235
申请日：2002-03-27
申请人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
发明人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/0332 , H01L21/32139 , H01L27/115
摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.
摘要翻译：用于MirrorBit（R）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质材料。植入第一和第二位线，并存放字线材料。硬掩模材料沉积在字线材料上。硬掩模材料是具有沉积而不是生长的特征的材料。光致抗蚀剂材料沉积在字线材料上并被图案化以形成图案化的硬掩模。去除图案化的光致抗蚀剂材料。使用图案化的硬掩模处理字线材料以形成字线。去除图案化的硬掩模材料。

10. 发明授权

US06479348B1 Method of making memory wordline hard mask extension 有权
标题翻译：制作内存字线硬掩模扩展的方法
公开(公告)号：US06479348B1
公开(公告)日：2002-11-12
申请号：US10109516
申请日：2002-08-27
申请人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
发明人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.
摘要翻译：提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。字线材料和硬掩模材料沉积在字线材料上。光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。然后去除图案化的光致抗蚀剂。硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

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