专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07167517B2 Analog N-tap FIR receiver equalizer 有权
标题翻译：模拟N抽头FIR接收均衡器
公开(公告)号：US07167517B2
公开(公告)日：2007-01-23
申请号：US09863081
申请日：2001-05-22
申请人： Ramin Farjad-Rad , Thomas H. Lee
发明人： Ramin Farjad-Rad , Thomas H. Lee
IPC分类号： H03H7/40
CPC分类号： H03L7/14 , H03H15/00 , H03L7/087 , H04L25/0307 , H04L2025/03477
摘要： An equalizer includes plural samplers for sampling an incoming input data stream according to plural phases of a sampling clock, each sampler producing a data sample. Operating in the analog domain, a multi-tap finite impulse response (FIR) filter weights the data samples and combines the weighted data samples to produce a filtered data bit. The filtered data bits thus form an equalized output data stream. The equalizer can compensate for characteristics of a communications channel, such as low-pass characteristics. The channel may carry high-speed, e.g., multi-gigabit per second, traffic.
摘要翻译：均衡器包括多个采样器，用于根据采样时钟的多个相位对输入的输入数据流进行采样，每个采样器产生数据采样。在模拟域中操作，多抽头有限脉冲响应（FIR）滤波器对数据采样进行加权，并组合加权数据采样以产生滤波数据位。滤波后的数据位因此形成均衡的输出数据流。均衡器可以补偿通信信道的特性，例如低通特性。该信道可以携带高速，例如，每秒千兆比特的流量。

2. 发明申请

US20110156044A1 DENSE ARRAYS AND CHARGE STORAGE DEVICES 审中-公开
标题翻译：渗透阵列和充电存储设备
公开(公告)号：US20110156044A1
公开(公告)日：2011-06-30
申请号：US13027113
申请日：2011-02-14
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul Michael Farmwald , Brad Herner
IPC分类号： H01L29/786 , H01L29/78
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

3. 发明申请

US20090195307A1 MULTIPLE-PATH POWER AMPLIFIER 有权
标题翻译：多路功率放大器
公开(公告)号：US20090195307A1
公开(公告)日：2009-08-06
申请号：US12025005
申请日：2008-02-02
申请人： Susan Luschas , Thomas H. Lee
发明人： Susan Luschas , Thomas H. Lee
IPC分类号： H03F3/68
CPC分类号： H03F1/0277 , H03F1/56 , H03F3/24 , H03F3/72 , H03F2200/387 , H03F2203/7236
摘要： An amplifier circuit and method for amplifying a signal efficiently over a plurality of power ranges. The amplifier circuit including a strong amplifier which is efficient over a first power range and a weak amplifier which is efficient over a second power range. An impedance transformation circuit is used for generating a higher potential and providing increased efficiency when the second range of power is present. A circuit biases active the strong amplifier when the first power range of is present and biases active the weak amplifier when the second power range is present.
摘要翻译：一种用于在多个功率范围上有效放大信号的放大器电路和方法。该放大器电路包括在第一功率范围内有效的强放大器和在第二功率范围内有效的弱放大器。当存在第二功率范围时，阻抗变换电路用于产生更高的电位并提供更高的效率。当存在第一功率范围时，电路偏置激活强放大器，并在存在第二功率范围时偏置弱放大器。

4. 发明授权

US07548040B2 Wireless battery charging of electronic devices such as wireless headsets/headphones 有权
标题翻译：电子设备如无线耳机/耳机的无线电池充电
公开(公告)号：US07548040B2
公开(公告)日：2009-06-16
申请号：US11494874
申请日：2006-07-28
申请人： Thomas H. Lee , Arthur J. Collmeyer , Dickson T. Wong
发明人： Thomas H. Lee , Arthur J. Collmeyer , Dickson T. Wong
IPC分类号： H02J7/00
CPC分类号： H04R1/1025 , H04R1/1016 , H04R2420/07
摘要： This disclosure relates to wireless battery charging of electronic devices such as wireless headsets/headphones. In one embodiment, an electronic device is provided comprising a speaker comprising a coil, and the coil is operative both to cause the speaker to produce sound and to receive energy transferred to the coil via inductive coupling. The received energy is used to recharge a rechargeable battery in the electronic device. In other embodiments, the coil used to receive the energy that recharges the battery is received by a coil other than the coil in the speaker.
摘要翻译：本公开涉及诸如无线耳机/耳机之类的电子设备的无线电池充电。在一个实施例中，提供一种电子设备，其包括包括线圈的扬声器，并且线圈可操作以使扬声器产生声音并且经由感应耦合接收传递到线圈的能量。所接收的能量用于为电子设备中的可再充电电池充电。在其他实施例中，用于接收对电池充电的能量的线圈由扬声器中的线圈以外的线圈接收。

5. 发明授权

US07474159B2 Frequency calibration for frequency synthesizers 有权
标题翻译：频率合成器的频率校准
公开(公告)号：US07474159B2
公开(公告)日：2009-01-06
申请号：US11801218
申请日：2007-05-08
申请人： Stanley Wang , Thomas H. Lee
发明人： Stanley Wang , Thomas H. Lee
IPC分类号： H03L7/00
CPC分类号： H03L7/113 , H03L7/099 , H03L7/18
摘要： A calibration circuit (17) for calibrating a frequency synthesizer (10) having a voltage-controlled oscillator (VCO) (15) with a plurality of switched-capacitor arrays (CA1-CAn). The calibration circuit (17) counts a predetermined number of periods of the reference-clock signal (ref_clk) and divide-clock signal (div_clk) of the frequency synthesizer using a fast clock signal (fastclk). The fast-clock signal (fastclk) has a frequency greater than either the reference-clock signal (ref_clk) or the divide-clock signal (div_clk), enabling significantly faster calibration of the frequency synthesizer (10) than would be possible using the reference-clock signal (ref_clk). The calibration circuit (17) compares the count of the periods of the reference-clock signal (ref_clk) and the divide-clock signal (div_clk) and varies the tank signal of the VCO (VCO_tank_setting) until the count of the periods is substantially equal.
摘要翻译：一种用于校准具有多个开关电容阵列（CA1-CAn）的具有压控振荡器（VCO）（15）的频率合成器（10）的校准电路（17）。校准电路（17）使用快速时钟信号（fastclk）计数频率合成器的基准时钟信号（ref_clk）和分频时钟信号（div_clk）的预定数量的周期。快速时钟信号（fastclk）的频率大于参考时钟信号（ref_clk）或分频时钟信号（div_clk），能够使频率合成器（10）的校准能够比使用参考时钟信号时钟信号（ref_clk）。校准电路（17）比较参考时钟信号（ref_clk）和分频时钟信号（div_clk）的周期的计数，并改变VCO的VCO信号（VCO_tank_setting），直到周期的计数基本相等。

6. 发明申请

US20080278247A1 Calibration of Voltage Controlled Oscillators 有权
公开(公告)号：US20080278247A1
公开(公告)日：2008-11-13
申请号：US12171277
申请日：2008-07-10
申请人： Stanley Wang , Bendik Kleveland , Thomas H. Lee
发明人： Stanley Wang , Bendik Kleveland , Thomas H. Lee
IPC分类号： H03B1/04
CPC分类号： H03L7/099
摘要： A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

7. 发明申请

US20080205122A1 MRAM MEMORY CONDITIONING 失效
标题翻译： MRAM内存条件
公开(公告)号：US20080205122A1
公开(公告)日：2008-08-28
申请号：US11678346
申请日：2007-02-23
申请人： Eric J. Salter , Mark F. Deherrera , Thomas H. Lee
发明人： Eric J. Salter , Mark F. Deherrera , Thomas H. Lee
IPC分类号： G11C11/02
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： According to an example embodiment, a method (500) includes applying a magnetic field to an array of Magnetic Tunnel Junction (MTJ) bits, a magnitude of the magnetic field sufficient to eliminate a stuck-at-mid condition exhibited by one of the MTJ bits without causing other ones of the MTJ bits to develop the stuck-at-mid condition.
摘要翻译：根据示例性实施例，一种方法（500）包括将磁场施加到磁隧道结（MTJ）位的阵列，所述磁场的大小足以消除由MTJ中的一个所展现的中间状态位，而不会导致MTJ位中的其他位发展到中间状态。

8. 发明授权

US07308065B2 Delay locked loop circuitry for clock delay adjustment 失效
标题翻译：延迟锁定环电路，用于时钟延迟调整
公开(公告)号：US07308065B2
公开(公告)日：2007-12-11
申请号：US11406557
申请日：2006-04-18
申请人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
发明人： Kevin S. Donnelly , Pak Shing Chau , Mark A. Horowitz , Thomas H. Lee , Mark G. Johnson , Benedict C. Lau , Leung Yu , Bruno W. Garlepp , Yiu-Fai Chan , Jun Kim , Chanh Vi Tran , Donald C. Stark , Nhat M. Nguyen
IPC分类号： H03D3/24 , H03L7/06
CPC分类号： H03K5/133 , G06F1/10 , G11C7/22 , G11C7/222 , H03K5/2481 , H03K2005/00026 , H03K2005/00032 , H03K2005/00052 , H03K2005/00208 , H03L7/07 , H03L7/0805 , H03L7/0812 , H03L7/0814 , H04L7/0008 , H04L7/0025 , H04L7/0037
摘要： A receiver adapted to be coupled to a data bus and configured to receive data in accordance with a receive clock includes first and second delay-locked loops. The first delay-locked loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay-locked loop is coupled to the first delay-locked loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.
摘要翻译：适于耦合到数据总线并被配置为根据接收时钟接收数据的接收机包括第一和第二延迟锁定环路。第一延迟锁定环路被配置为从第一参考时钟产生多个相位矢量，并且第二延迟锁定环路耦合到第一延迟锁定环路并且被配置为从至少一个相位矢量生成接收时钟从所述多个相位矢量中选择并具有第二参考时钟。

9. 发明授权

US07129538B2 Dense arrays and charge storage devices 有权
公开(公告)号：US07129538B2
公开(公告)日：2006-10-31
申请号：US10842008
申请日：2004-05-10
申请人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
发明人： Thomas H. Lee , Vivek Subramanian , James M. Cleeves , Andrew J. Walker , Christopher Petti , Igor G. Kouznetzov , Mark G. Johnson , Paul M. Farmwald , Brad Herner
IPC分类号： H01L29/788
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

10. 发明授权

US06963626B1 Noise-reducing arrangement and method for signal processing 失效
标题翻译：降噪装置及信号处理方法
公开(公告)号：US06963626B1
公开(公告)日：2005-11-08
申请号：US09310598
申请日：1999-05-12
申请人： K. Derek Shaeffer , Theresa H. Meng , Thomas H. Lee , Sydney Reader
发明人： K. Derek Shaeffer , Theresa H. Meng , Thomas H. Lee , Sydney Reader
IPC分类号： H04B1/04 , H04B1/10 , H04B1/30
CPC分类号： H04B1/0475 , H04B1/30
摘要： A communication system uses analog and digital circuits along the same data path in a manner that permits the analog circuitry to avoid adverse affects caused by the digital circuitry. Consistent with one embodiment directed to a signal processing system that detects faint incoming signals, the analog and digital circuits are implemented on a single piece of silicon. In such signal processing systems, noise generated by digital processing blocks can degrade the performance of sensitive analog portions. The effective noise is reduced by causing the analog and digital portions of the system to function during separate time intervals. The noise-generating portions of the system may then be turned off during a first data-communication interval while the analog block operates. The data acquired during this period is stored for subsequent processing by the digital portion during a second shorter data-communication interval. Other aspects are applicable to reception arrangements in which part of the incoming signal may be disregarded without significant degradation in performance of the rest of the system, and other aspects are directed to transmission arrangements in which the inverse of the above reception arrangement is used.
摘要翻译：通信系统以允许模拟电路避免由数字电路引起的不利影响的方式沿同一数据路径使用模拟和数字电路。与针对检测微弱输入信号的信号处理系统的一个实施例一致，模拟和数字电路在单片硅片上实现。在这种信号处理系统中，由数字处理块产生的噪声可能降低敏感模拟部分的性能。通过使系统的模拟和数字部分在分开的时间间隔内起作用，降低了有效噪声。然后可以在模拟块操作期间的第一数据通信间隔期间关闭系统的噪声产生部分。在该时段期间获取的数据被存储用于在第二较短的数据通信间隔期间由数字部分进行后续处理。其他方面适用于其中输入信号的一部分可以被忽略而不会使系统的其余部分的性能显着降低的接收装置，并且其它方面涉及使用上述接收装置的反向的传输布置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式