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1. 发明授权

US06309924B1 Method of forming self-limiting polysilicon LOCOS for DRAM cell 失效
标题翻译： DRAM单元形成自限多晶硅LOCOS的方法
公开(公告)号：US06309924B1
公开(公告)日：2001-10-30
申请号：US09585898
申请日：2000-06-02
申请人： Ramachandra Divakaruni , Jack Allan Mandelman , Irene Lennox McStay , Larry A. Nesbit , Carl John Radens , Helmut Horst Tews
发明人： Ramachandra Divakaruni , Jack Allan Mandelman , Irene Lennox McStay , Larry A. Nesbit , Carl John Radens , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L27/10867
摘要： A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.
摘要翻译：一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。首先在硅衬底中形成DRAM沟槽。然后，氮化物衬垫沉积在硅沟槽壁上。氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层上。然后将一层非晶硅沉积在氮化物衬垫上。在非晶硅的氧化表面上沉积氮化硅层。在沟槽的下部形成抗蚀剂，去除在非晶硅顶部的暴露的氮化硅层，留下非晶硅层的上部。然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环。非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

2. 发明授权

US06544855B1 Process flow for sacrificial collar with polysilicon void 有权
标题翻译：具有多晶硅空隙的牺牲环的工艺流程
公开(公告)号：US06544855B1
公开(公告)日：2003-04-08
申请号：US10041779
申请日：2001-10-19
申请人： Helmut Horst Tews , Rolf Weis , Irene Lennox McStay
发明人： Helmut Horst Tews , Rolf Weis , Irene Lennox McStay
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L27/10867
摘要： A process for forming a sacrificial collar on the top portion of a deep trench (114) of a semiconductor wafer (100). A nitride layer (116) is deposited within the trenches (114). A semiconductor material layer (120) is deposited over the nitride layer (116) and is etched back to a predetermined height (A) below the substrate 112 top surface. A semiconductor material plug (132) is formed at the top surface of the recessed semiconductor material layer (120), leaving a void (133) in the bottom of each trench (114). An oxide layer (134) and nitride layer (136) are formed over the wafer (100) and trenches (116), and the semiconductor material plug (132) and semiconductor material layer (120) are removed from the bottom of the trenches (116).
摘要翻译：一种用于在半导体晶片（100）的深沟槽（114）的顶部上形成牺牲套环的工艺。氮化物层（116）沉积在沟槽（114）内。半导体材料层（120）沉积在氮化物层（116）上并且被回蚀刻到衬底112顶表面下方的预定高度（A）。半导体材料插塞（132）形成在凹陷半导体材料层（120）的顶表面处，在每个沟槽（114）的底部留下空隙（133）。在晶片（100）和沟槽（116）之上形成氧化物层（134）和氮化物层（136），半导体材料插塞（132）和半导体材料层（120）从沟槽的底部 116）。

3. 发明申请

US20110278680A1 Strained Semiconductor Device and Method of Making the Same 有权
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US20110278680A1
公开(公告)日：2011-11-17
申请号：US13193692
申请日：2011-07-29
申请人： Helmut Horst Tews , Andre Schenk
发明人： Helmut Horst Tews , Andre Schenk
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L27/1203 , H01L29/66477 , H01L29/6653 , H01L29/66636 , H01L29/7834
摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.
摘要翻译：在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。栅电极与半导体本体电绝缘。沿着栅电极的侧壁形成第一侧壁间隔物。邻近第一侧壁间隔件形成牺牲侧壁间隔物。牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。

4. 发明申请

US20100330771A1 Moisture Barrier Capacitors in Semiconductor Components 审中-公开
标题翻译：半导体元件中的阻水电容器
公开(公告)号：US20100330771A1
公开(公告)日：2010-12-30
申请号：US12876866
申请日：2010-09-07
申请人： Hans-Joachim Barth , Helmut Horst Tews
发明人： Hans-Joachim Barth , Helmut Horst Tews
IPC分类号： H01L21/02
CPC分类号： H01L28/75 , G06F17/5068 , H01L21/76897 , H01L22/14 , H01L23/5223 , H01L23/5226 , H01L23/562 , H01L23/585 , H01L27/0611 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.
摘要翻译：公开了在半导体部件上形成防潮电容器的结构和方法。电容器位于半导体芯片的周围，并且包括电连接到电压节点的内板，具有用于电连接到不同电压节点的翅片的外板。

5. 发明授权

US07157328B2 Selective etching to increase trench surface area 有权
标题翻译：选择性蚀刻以增加沟槽表面积
公开(公告)号：US07157328B2
公开(公告)日：2007-01-02
申请号：US11047312
申请日：2005-01-31
申请人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
发明人： Helmut Horst Tews , Stephan Kudelka , Kenneth T. Settlemyer
IPC分类号： H01L21/8242
CPC分类号： H01L21/30604 , H01L29/66181
摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.
摘要翻译：在衬底中形成的沟槽的壁的表面积增加。阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角沟渠墙壁的交叉点。

6. 发明授权

US06967147B1 Nitrogen implantation using a shadow effect to control gate oxide thickness in DRAM semiconductor 失效
标题翻译：使用阴影效应的氮注入来控制DRAM半导体中的栅极氧化物厚度
公开(公告)号：US06967147B1
公开(公告)日：2005-11-22
申请号：US09714356
申请日：2000-11-16
申请人： Helmut Horst Tews , Jochen Beintner
发明人： Helmut Horst Tews , Jochen Beintner
IPC分类号： H01L20060101 , H01L21/265 , H01L21/28 , H01L21/76 , H01L21/8234 , H01L21/8242 , H01L27/06
CPC分类号： H01L21/823462 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/823481 , H01L27/0629 , H01L27/10873 , Y10S438/981
摘要： Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers is used to create a “shadow effect” or area, which limits the nitrogen dose close to the edges of the active area. The reduction of nitrogen dose leads to an increased gate oxide thickness at the active area (AA) adjacent to the shallow trench, increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.
摘要翻译：用于通过使用氮注入并入不同厚度的栅极氧化物来形成用于DRAMS的双栅极氧化物的工艺。使用倾斜的氮气注入或氮化物间隔物来产生“阴影效应”或区域，这限制了接近有效区域边缘的氮剂量。氮剂量的减少导致在与浅沟槽相邻的有源区（AA）处的栅极氧化物厚度增加，增加了寄生角装置的阈值并且减小了副Vt（阈值电压）和结漏电。

7. 发明授权

US06677197B2 High aspect ratio PBL SiN barrier formation 有权
标题翻译：高纵横比PBL SiN阻挡层形成
公开(公告)号：US06677197B2
公开(公告)日：2004-01-13
申请号：US10032040
申请日：2001-12-31
申请人： Stephan Kudelka , Helmut Horst Tews
发明人： Stephan Kudelka , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L29/66181
摘要： In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.
摘要翻译：在制备通常需要在瓶形成后形成套环的亚100nm研磨剂制备DT DRAM的方法中，通过形成高面积比PBL SiN阻挡层来改进提供轴环第一方案，该方法包括：a）在SiN结点沉积和DT多晶硅填充之后的半导体结构; b）沉积多层缓冲LOCOS（PBL）Si衬垫; c）使PBL衬里氧化形成衬垫氧化物并沉积SiN阻挡层; d）沉积硅掩模衬垫; e）使用p-掺杂剂对DT进行高定向离子注入（I / I）; f）使用SiN上的蚀刻停止对未被注入的Si的选择性湿蚀刻; g）使步骤f）的产物在衬垫氧化物上具有蚀刻停止层的SiN湿蚀刻; h）影响衬垫氧化物上的停止的Si衬层蚀刻; i）氧化PBL Si衬垫并影响势垒SiN条; j）提供DT多晶硅填充物进行多化学机械抛光。

8. 发明授权

US08569820B2 Capacitor having a plurality of parallel conductive members 有权
标题翻译：具有多个平行导电构件的电容器
公开(公告)号：US08569820B2
公开(公告)日：2013-10-29
申请号：US13344714
申请日：2012-01-06
申请人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
发明人： Hans-Joachim Barth , Erwin Ruderer , Alexander Von Glasow , Philipp Riess , Erdem Kaltalioglu , Peter Baumgartner , Thomas Benetik , Helmut Horst Tews
IPC分类号： H01L27/108
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

9. 发明授权

US07767562B2 Method of implanting using a shadow effect 有权
标题翻译：使用阴影效果进行植入的方法
公开(公告)号：US07767562B2
公开(公告)日：2010-08-03
申请号：US11235330
申请日：2005-09-26
申请人： Helmut Horst Tews , Jochen Beintner
发明人： Helmut Horst Tews , Jochen Beintner
IPC分类号： H01L21/425
CPC分类号： H01L21/823462 , H01L21/26506 , H01L21/26586 , H01L21/2822 , H01L21/823481 , H01L27/0629 , H01L27/10873 , Y10S438/981
摘要： A semiconductor body has a first portion, a second portion, and an active area located between the first portion and the second portion. The first portion and the second portion are a shallow trench isolation region having an exposed surface extending above the surface of the active area. A first ion implantation is performed at a first angle such that a first shaded area defined by the exposed surface of the first portion and the first angle is exposed to fewer ions than a first unshaded area. A second ion implantation is performed at a second angle such that a second shaded area defined by the exposed surface of the second portion and the second angle is exposed to fewer ions than a second unshaded area.
摘要翻译：半导体本体具有位于第一部分和第二部分之间的第一部分，第二部分和有源区域。第一部分和第二部分是具有在有源区域的表面上方延伸的暴露表面的浅沟槽隔离区域。以第一角度执行第一离子注入，使得由第一部分的暴露表面限定的第一阴影区域和第一角度暴露于比第一未阴影区域更少的离子。以第二角度执行第二离子注入，使得由第二部分的暴露表面限定的第二阴影区域和第二角度暴露于比第二未阴影区域更少的离子。

10. 发明申请

US20090160020A1 Moisture Barrier Capacitors in Semiconductor Components 有权
标题翻译：半导体元件中的阻水电容器
公开(公告)号：US20090160020A1
公开(公告)日：2009-06-25
申请号：US11962395
申请日：2007-12-21
申请人： Hans-Joachim Barth , Helmut Horst Tews
发明人： Hans-Joachim Barth , Helmut Horst Tews
IPC分类号： H01L29/92 , H01L21/02 , H01L21/66
CPC分类号： H01L28/75 , G06F17/5068 , H01L21/76897 , H01L22/14 , H01L23/5223 , H01L23/5226 , H01L23/562 , H01L23/585 , H01L27/0611 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.
摘要翻译：公开了在半导体部件上形成防潮电容器的结构和方法。电容器位于半导体芯片的周围，并且包括电连接到电压节点的内板，具有用于电连接到不同电压节点的翅片的外板。

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