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1. 发明授权

US06576565B1 RTCVD process and reactor for improved conformality and step-coverage 有权
标题翻译： RTCVD工艺和反应器，以提高保形性和阶梯覆盖率
公开(公告)号：US06576565B1
公开(公告)日：2003-06-10
申请号：US10075152
申请日：2002-02-14
申请人： Ashima Chakravarti , Oleg Gluschenkov , Irene Lennox McStay
发明人： Ashima Chakravarti , Oleg Gluschenkov , Irene Lennox McStay
IPC分类号： H01L2131
CPC分类号： C23C16/45572 , C23C16/045 , C23C16/481 , C23C16/52 , H01L21/02164 , H01L21/02271 , H01L21/31612 , H01L21/3185 , H01L21/67109 , H01L21/67115 , H01L27/10861
摘要： An apparatus (110) and method for depositing material on a semiconductor wafer with non-planar structures (114). The wafer (114) is positioned in a chamber (111), and reactive gases (132) are introduced into the chamber (111). The gases (132) and wafer (114) are heated, wherein the gas (132) temperature in the process chamber (111) and in the vicinity of the wafer (114) surface is lower than the temperature of the wafer (114) surface. A material is deposited on the wafer (114) surface using chemical vapor deposition. A gas cooler may be utilized to lower the temperature of the reactive gases (132) while the wafer (114) is heated.
摘要翻译：一种用于在具有非平面结构（114）的半导体晶片上沉积材料的装置（110）和方法。晶片（114）定位在室（111）中，反应气体（132）被引入室（111）中。加热气体（132）和晶片（114），其中处理室（111）中和晶片（114）表面附近的气体（132）温度低于晶片（114）表面的温度。使用化学气相沉积将材料沉积在晶片（114）表面上。当加热晶片（114）时，气体冷却器可用于降低反应气体（132）的温度。

2. 发明授权

US06544855B1 Process flow for sacrificial collar with polysilicon void 有权
标题翻译：具有多晶硅空隙的牺牲环的工艺流程
公开(公告)号：US06544855B1
公开(公告)日：2003-04-08
申请号：US10041779
申请日：2001-10-19
申请人： Helmut Horst Tews , Rolf Weis , Irene Lennox McStay
发明人： Helmut Horst Tews , Rolf Weis , Irene Lennox McStay
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L27/10867
摘要： A process for forming a sacrificial collar on the top portion of a deep trench (114) of a semiconductor wafer (100). A nitride layer (116) is deposited within the trenches (114). A semiconductor material layer (120) is deposited over the nitride layer (116) and is etched back to a predetermined height (A) below the substrate 112 top surface. A semiconductor material plug (132) is formed at the top surface of the recessed semiconductor material layer (120), leaving a void (133) in the bottom of each trench (114). An oxide layer (134) and nitride layer (136) are formed over the wafer (100) and trenches (116), and the semiconductor material plug (132) and semiconductor material layer (120) are removed from the bottom of the trenches (116).
摘要翻译：一种用于在半导体晶片（100）的深沟槽（114）的顶部上形成牺牲套环的工艺。氮化物层（116）沉积在沟槽（114）内。半导体材料层（120）沉积在氮化物层（116）上并且被回蚀刻到衬底112顶表面下方的预定高度（A）。半导体材料插塞（132）形成在凹陷半导体材料层（120）的顶表面处，在每个沟槽（114）的底部留下空隙（133）。在晶片（100）和沟槽（116）之上形成氧化物层（134）和氮化物层（136），半导体材料插塞（132）和半导体材料层（120）从沟槽的底部 116）。

3. 发明授权

US06309924B1 Method of forming self-limiting polysilicon LOCOS for DRAM cell 失效
标题翻译： DRAM单元形成自限多晶硅LOCOS的方法
公开(公告)号：US06309924B1
公开(公告)日：2001-10-30
申请号：US09585898
申请日：2000-06-02
申请人： Ramachandra Divakaruni , Jack Allan Mandelman , Irene Lennox McStay , Larry A. Nesbit , Carl John Radens , Helmut Horst Tews
发明人： Ramachandra Divakaruni , Jack Allan Mandelman , Irene Lennox McStay , Larry A. Nesbit , Carl John Radens , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L27/10867
摘要： A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.
摘要翻译：一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。首先在硅衬底中形成DRAM沟槽。然后，氮化物衬垫沉积在硅沟槽壁上。氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层上。然后将一层非晶硅沉积在氮化物衬垫上。在非晶硅的氧化表面上沉积氮化硅层。在沟槽的下部形成抗蚀剂，去除在非晶硅顶部的暴露的氮化硅层，留下非晶硅层的上部。然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环。非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

4. 发明授权

US06444516B1 Semi-insulating diffusion barrier for low-resistivity gate conductors 失效
标题翻译：用于低电阻率栅极导体的半绝缘扩散阻挡层
公开(公告)号：US06444516B1
公开(公告)日：2002-09-03
申请号：US09613197
申请日：2000-07-07
申请人： Lawrence Alfred Clevenger , Jack A. Mandelman , Rajarao Jammy , Oleg Gluschenkov , Irene Lennox McStay , Kwong Hon Wong , Johnathan Faltermeier
发明人： Lawrence Alfred Clevenger , Jack A. Mandelman , Rajarao Jammy , Oleg Gluschenkov , Irene Lennox McStay , Kwong Hon Wong , Johnathan Faltermeier
IPC分类号： H01L218234
CPC分类号： H01L21/28044 , H01L29/4941
摘要： A gate structure for a semiconductor device, and particularly a MOSFET for such applications as CMOS technology. The gate structure entails an electrical insulating layer on a semiconductor substrate, over which a polysilicon gate electrode is formed. The gate structure further includes a gate conductor that is electrically connected with the gate electrode through a diffusion barrier layer having semi-insulating properties. The composition and thickness of the diffusion barrier layer are tailored so that the barrier layer is effective to block diffusion and intermixing between the gate conductor and polysilicon gate electrode, yet provides sufficient capacitive coupling and/or current leakage so as not to significantly increase the gate propagation delay of the gate structure.
摘要翻译：用于半导体器件的栅极结构，特别是用于诸如CMOS技术的应用的MOSFET。栅结构需要在半导体衬底上形成电绝缘层，形成多晶硅栅电极。栅极结构还包括通过具有半绝缘性质的扩散阻挡层与栅电极电连接的栅极导体。调整扩散阻挡层的组成和厚度，使得阻挡层有效地阻挡栅极导体和多晶硅栅电极之间的扩散和混合，但提供足够的电容耦合和/或电流泄漏，从而不显着增加栅极门结构的传播延迟。

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