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1. 发明申请

US20060004887A1 Method and device for generating distributed java applications by means of a central xml configuration file 审中-公开
标题翻译：通过中央xml配置文件生成分布式Java应用程序的方法和设备
公开(公告)号：US20060004887A1
公开(公告)日：2006-01-05
申请号：US10530213
申请日：2002-04-04
申请人： Andre Schenk
发明人： Andre Schenk
IPC分类号： G06F17/30
CPC分类号： G06F8/30
摘要： There is disclosed a method and a device for generating distributed applications for each level in a multi-level database environment, comprising: receiving an integrated configuration code comprising code sections for all information required for generating an application in each of said levels, parsing all code sections in said integrated configuration code required for at least one level of said multi-level environment, extracting said parsed code sections for said at least one level, and converting said extracted code sections into level-specific application code for each extracted level.
摘要翻译：公开了一种用于在多级数据库环境中为每个级别生成分布式应用的方法和设备，包括：接收集成配置代码，其包括用于在每个所述级别中生成应用所需的所有信息的代码段，解析所有代码为所述多级环境的至少一个级别所需的所述集成配置代码中的部分，提取用于所述至少一个级别的所述解析的代码段，并且将所提取的代码段转换为针对每个提取的级别的级别特定应用代码。

2. 发明授权

US06919264B2 Method for the solder-stop structuring of elevations on wafers 失效
标题翻译：阻焊结构在晶圆上的方法
公开(公告)号：US06919264B2
公开(公告)日：2005-07-19
申请号：US10656042
申请日：2003-09-05
申请人： Axel Brintzinger , Ingo Uhlendorf , Andre Schenk , Alexander Wollanke
发明人： Axel Brintzinger , Ingo Uhlendorf , Andre Schenk , Alexander Wollanke
IPC分类号： H01L21/44 , H01L21/60 , H01L23/485
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/11902 , H01L2224/13099 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2224/0401
摘要： A method is provided for the solder-stop structuring of elevations on wafers, such as 3D contact structures in the form of resilient or compliant contact bumps, which are connected electrically via a metallization layer to a bonding pad on the wafer, the metallization layer extending over the 3D structure and consisting of a Cu/Ni layer which is covered with a Au layer. The present invention provides a method for the solder-stop structuring of elevations on wafers which can be implemented simply and reliably to produce a reliable solder stop and good flank protection of the 3D structure. According to the invention, a resist is deposited on the tip of a 3D structure and a solder stop layer is then deposited over the metallization, including the resist. The resist on the tip of the 3D structure, including the solder stop layer covering the resist, is subsequently removed so that the Au layer on the tip of the 3D structure is exposed.
摘要翻译：提供了一种用于焊接停止构造晶片上的高度的方法，例如以弹性或柔性接触凸块的形式的3D接触结构，其通过金属化层电连接到晶片上的接合焊盘，金属化层延伸由三维结构构成，由Au层覆盖的Cu / Ni层构成。本发明提供了一种用于焊接停止构造晶片上的高程的方法，其可以简单可靠地实现以产生可靠的焊料停止和3D结构的良好的侧面保护。根据本发明，抗蚀剂沉积在3D结构的尖端上，然后在包括抗蚀剂的金属化层上沉积阻焊层。随后去除3D结构的尖端上的抗蚀剂，包括覆盖抗蚀剂的阻焊层，使得3D结构的尖端上的Au层被暴露。

3. 发明授权

US06665641B1 Speech synthesis using concatenation of speech waveforms 有权
标题翻译：语音合成采用语音波形串联
公开(公告)号：US06665641B1
公开(公告)日：2003-12-16
申请号：US09438603
申请日：1999-11-12
申请人： Geert Coorman , Filip Deprez , Mario De Bock , Justin Fackrell , Steven Leys , Peter Rutten , Jan DeMoortel , Andre Schenk , Bert Van Coile
发明人： Geert Coorman , Filip Deprez , Mario De Bock , Justin Fackrell , Steven Leys , Peter Rutten , Jan DeMoortel , Andre Schenk , Bert Van Coile
IPC分类号： G10L1308
CPC分类号： G10L13/07 , G10L13/06
摘要： A high quality speech synthesizer in various embodiments concatenates speech waveforms referenced by a large speech database. Speech quality is further improved by speech unit selection and concatenation smoothing.
摘要翻译：各种实施例中的高质量语音合成器连接由大语音数据库引用的语音波形。通过语音单元选择和级联平滑进一步提高语音质量。

4. 发明申请

US20110278680A1 Strained Semiconductor Device and Method of Making the Same 有权
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US20110278680A1
公开(公告)日：2011-11-17
申请号：US13193692
申请日：2011-07-29
申请人： Helmut Horst Tews , Andre Schenk
发明人： Helmut Horst Tews , Andre Schenk
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L27/1203 , H01L29/66477 , H01L29/6653 , H01L29/66636 , H01L29/7834
摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.
摘要翻译：在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。栅电极与半导体本体电绝缘。沿着栅电极的侧壁形成第一侧壁间隔物。邻近第一侧壁间隔件形成牺牲侧壁间隔物。牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。

5. 发明申请

US20070057324A1 Strained semiconductor device and method of making the same 有权
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US20070057324A1
公开(公告)日：2007-03-15
申请号：US11224825
申请日：2005-09-13
申请人： Helmut Tews , Andre Schenk
发明人： Helmut Tews , Andre Schenk
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L27/1203 , H01L29/66477 , H01L29/6653 , H01L29/66636 , H01L29/7834
摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.
摘要翻译：在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。栅电极与半导体本体电绝缘。沿着栅电极的侧壁形成第一侧壁间隔物。邻近第一侧壁间隔件形成牺牲侧壁间隔物。牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。

6. 发明授权

US08003470B2 Strained semiconductor device and method of making the same 有权
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US08003470B2
公开(公告)日：2011-08-23
申请号：US11224825
申请日：2005-09-13
申请人： Helmut Horst Tews , Andre Schenk
发明人： Helmut Horst Tews , Andre Schenk
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L27/1203 , H01L29/66477 , H01L29/6653 , H01L29/66636 , H01L29/7834
摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.
摘要翻译：在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。栅电极与半导体本体电绝缘。沿着栅电极的侧壁形成第一侧壁间隔物。邻近第一侧壁间隔件形成牺牲侧壁间隔物。牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。

7. 发明授权

US07219060B2 Speech synthesis using concatenation of speech waveforms 有权
标题翻译：语音合成采用语音波形串联
公开(公告)号：US07219060B2
公开(公告)日：2007-05-15
申请号：US10724659
申请日：2003-12-01
申请人： Geert Coorman , Filip Deprez , Mario De Bock , Justin Fackrell , Steven Leys , Peter Rutten , Jan De Moortel , Andre Schenk , Bert Van Coile
发明人： Geert Coorman , Filip Deprez , Mario De Bock , Justin Fackrell , Steven Leys , Peter Rutten , Jan De Moortel , Andre Schenk , Bert Van Coile
IPC分类号： G10L13/02
CPC分类号： G10L13/07 , G10L13/06
摘要： A high quality speech synthesizer in various embodiments concatenates speech waveforms referenced by a large speech database. Speech quality is further improved by speech unit selection and concatenation smoothing.
摘要翻译：各种实施例中的高质量语音合成器连接由大型语音数据库引用的语音波形。通过语音单元选择和级联平滑进一步提高语音质量。

8. 发明授权

US08624334B2 Strained semiconductor device and method of making the same 有权
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US08624334B2
公开(公告)日：2014-01-07
申请号：US13193692
申请日：2011-07-29
申请人： Helmut Horst Tews , Andre Schenk
发明人： Helmut Horst Tews , Andre Schenk
IPC分类号： H01L27/088
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L27/1203 , H01L29/66477 , H01L29/6653 , H01L29/66636 , H01L29/7834
摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.
摘要翻译：在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。栅电极与半导体本体电绝缘。沿着栅电极的侧壁形成第一侧壁间隔物。邻近第一侧壁间隔件形成牺牲侧壁间隔物。牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。

9. 发明申请

US20070249128A1 Ultraviolet (UV) Radiation Treatment Methods for Subatmospheric Chemical Vapor Deposition (SACVD) of Ozone-Tetraethoxysilane (O3-TEOS) 审中-公开
标题翻译：臭氧四乙氧基硅烷（O3-TEOS）的大气压化学气相沉积（SACVD）的紫外（UV）辐射处理方法
公开(公告)号：US20070249128A1
公开(公告)日：2007-10-25
申请号：US11379285
申请日：2006-04-19
申请人： Junjung Kim , JaeEon Park , Johnny Widodo , Andre Schenk , Alois Gutmann , Roland Hampp
发明人： Junjung Kim , JaeEon Park , Johnny Widodo , Andre Schenk , Alois Gutmann , Roland Hampp
IPC分类号： H01L21/473
CPC分类号： H01L21/76825 , H01L21/02126 , H01L21/02216 , H01L21/02277 , H01L21/3105 , H01L21/31612
摘要： Dielectric layers are formed on a substrate by performing Subatmospheric Chemical Vapor Deposition (SACVD) of ozone-tetraethoxysilane (O3-TEOS) to form a layer of O3-TEOS on the substrate, and treating the layer of O3-TEOS with ultraviolet (UV) radiation. The UV radiation treatment can increase the tensile stress in the O3-TEOS layer by reducing the amount of water in the layer. Moreover, the UV treatment may also reduce the amount of silanol in the O3-TEOS layer, which can also increase reliability of the device.
摘要翻译：通过执行臭氧四乙氧基硅烷（O 3 3 -TEOS）的低气压化学气相沉积（SACVD）在基底上形成介电层，以形成一层O 3 3 -TEOS 底物，并用紫外线（UV）辐射处理O 3 -TEOS层。 UV辐射处理可以通过减少层中的水的量来增加O 3/3层的拉伸应力。此外，紫外线处理也可以减少O 3 3 -TEOS层中的硅烷醇的量，这也可以提高装置的可靠性。

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