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1. 发明授权

US06309924B1 Method of forming self-limiting polysilicon LOCOS for DRAM cell 失效
标题翻译： DRAM单元形成自限多晶硅LOCOS的方法
公开(公告)号：US06309924B1
公开(公告)日：2001-10-30
申请号：US09585898
申请日：2000-06-02
申请人： Ramachandra Divakaruni , Jack Allan Mandelman , Irene Lennox McStay , Larry A. Nesbit , Carl John Radens , Helmut Horst Tews
发明人： Ramachandra Divakaruni , Jack Allan Mandelman , Irene Lennox McStay , Larry A. Nesbit , Carl John Radens , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/10861 , H01L27/10867
摘要： A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer. A layer of amorphous silicon is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.
摘要翻译：一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。首先在硅衬底中形成DRAM沟槽。然后，氮化物衬垫沉积在硅沟槽壁上。氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层上。然后将一层非晶硅沉积在氮化物衬垫上。在非晶硅的氧化表面上沉积氮化硅层。在沟槽的下部形成抗蚀剂，去除在非晶硅顶部的暴露的氮化硅层，留下非晶硅层的上部。然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环。非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

2. 发明申请

US20080048259A1 Method for Reducing Defects in Buried Oxide Layers of Silicon on Insulator Substrates 审中-公开
标题翻译：减少硅绝缘体衬底氧化层缺陷的方法
公开(公告)号：US20080048259A1
公开(公告)日：2008-02-28
申请号：US11466480
申请日：2006-08-23
申请人： Kangguo Cheng , Ramachandra Divakaruni , Louis Lu-Chen Hsu , Jack Allan Mandelman
发明人： Kangguo Cheng , Ramachandra Divakaruni , Louis Lu-Chen Hsu , Jack Allan Mandelman
IPC分类号： H01L27/12
CPC分类号： H01L29/78603 , H01L29/66772 , H01L29/78609
摘要： A method and a structure for reducing defects in buried oxide layers of a silicon-on-insulator substrate. The method includes: generating a beam of infrared radiation of a selected wavelength; exposing a silicon-on-insulator substrate to the beam of infrared radiation, the substrate comprising a buried silicon dioxide layer between a lower layer of silicon and an upper layer of silicon; and wherein silicon has a transmittance of at least 95% at the selected wavelength and silicon dioxide has a transmittance of less than 80% at the selected wavelength.
摘要翻译：一种减少绝缘体上硅衬底的掩埋氧化物层缺陷的方法和结构。该方法包括：产生所选波长的红外辐射束; 将绝缘体上硅衬底暴露于所述红外辐射束，所述衬底包括在下层硅和硅上层之间的掩埋二氧化硅层; 并且其中硅在所选波长处具有至少95％的透射率，并且二氧化硅在所选择的波长处具有小于80％的透射率。

3. 发明授权

US07611931B2 Semiconductor structures with body contacts and fabrication methods thereof 有权
标题翻译：具有身体接触的半导体结构及其制造方法
公开(公告)号：US07611931B2
公开(公告)日：2009-11-03
申请号：US11928135
申请日：2007-10-30
申请人： Kangguo Cheng , Ramachandra Divakaruni , Jack Allan Mandelman
发明人： Kangguo Cheng , Ramachandra Divakaruni , Jack Allan Mandelman
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/0218 , H01L27/10841 , H01L27/10864 , H01L27/10891
摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact electrically coupling a semiconductor body and a semiconductor substrate of the SOI wafer. The semiconductor body includes a channel region for the access device of one of the vertical memory cells. The body contact, which extends through a buried dielectric layer of the SOI wafer, provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by etching a via that extends through the semiconductor body and buried dielectric layer of the SOI wafer and extends into the substrate and partially filling the via with a conductive material that electrically couples the semiconductor body with the substrate.
摘要翻译：一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括构建在绝缘体上半导体（SOI）晶片上的多个垂直存储器单元和电耦合SOI的半导体本体和半导体衬底的主体接触晶圆。半导体本体包括用于垂直存储单元之一的存取装置的通道区域。延伸穿过SOI晶片的掩埋介电层的主体接触件提供电流泄漏路径，其减少浮体对垂直存储单元的影响。可以通过蚀刻延伸穿过SOI晶片的半导体主体和埋入介质层的通孔来形成本体接触，并且延伸到衬底中并且用导电材料部分地填充通孔，所述导电材料使半导体本体与衬底电耦合。

4. 发明授权

US06767781B2 Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask 失效
标题翻译：使用线位线接触掩模形成垂直DRAM阵列的位线触点的结构和方法
公开(公告)号：US06767781B2
公开(公告)日：2004-07-27
申请号：US10667308
申请日：2003-09-23
申请人： Larry A. Nesbit , Jonathan E. Faltermeier , Ramachandra Divakaruni , Wolfgang Bergner
发明人： Larry A. Nesbit , Jonathan E. Faltermeier , Ramachandra Divakaruni , Wolfgang Bergner
IPC分类号： H01L218238
CPC分类号： H01L27/10885 , H01L21/76895 , H01L21/76897 , H01L27/10888
摘要： A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.
摘要翻译：使用位线接触掩模形成垂直DRAM阵列的位线接触的位线接触和方法。在该方法中，形成栅极导体线。在栅极导体线上沉积氧化物层，并且在氧化物层的部分上形成位线接触掩模。蚀刻位线接触掩模，并且在衬底上沉积硅层。位于硅层上的位线层被沉积。对位线层进行掩模和蚀刻操作。在硅层和位线（M0）层的非蚀刻部分的侧面上沉积M0金属以形成左和右位线。

5. 发明授权

US06686668B2 Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask 有权
公开(公告)号：US06686668B2
公开(公告)日：2004-02-03
申请号：US09764833
申请日：2001-01-17
申请人： Larry A. Nesbit , Johnathan E. Faltermeier , Ramachandra Divakaruni , Wolfgang Bergner
发明人： Larry A. Nesbit , Johnathan E. Faltermeier , Ramachandra Divakaruni , Wolfgang Bergner
IPC分类号： H01L27108
CPC分类号： H01L27/10885 , H01L21/76895 , H01L21/76897 , H01L27/10888
摘要： A bitline contact and method of forming bitline contact for a vertical DRAM array using a bitline contact mask. In the method, gate conductor lines are formed. An oxide layer is deposited over the gate conductor lines, and a bitline contact mask is formed over portions of the oxide layer. The bitline contact mask is etched, and a silicon layer is deposited on the substrate. A bitline layer is deposited on the silicon layer. A masking and etching operation is performed on the bitline layer. A M0 metal is deposited over the silicon layer and on sides of non etched portions of the bitline (M0) layer to form left and right bitlines.

6. 发明授权

US07569450B2 Semiconductor capacitors in hot (hybrid orientation technology) substrates 失效
标题翻译：热（混合取向技术）衬底中的半导体电容器
公开(公告)号：US07569450B2
公开(公告)日：2009-08-04
申请号：US11423284
申请日：2006-06-09
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L29/66931
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.
摘要翻译：半导体结构及其形成方法。半导体结构包括半导体衬底。半导体结构还包括在半导体衬底的顶部上的电绝缘区域。半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。半导体结构还包括在绝缘区域的顶部上的第二半导体区域。半导体结构还包括在第一半导体区域和半导体衬底中的电容器。半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。

7. 发明授权

US07919347B2 Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes 有权
标题翻译：制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构
公开(公告)号：US07919347B2
公开(公告)日：2011-04-05
申请号：US12349018
申请日：2009-01-06
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens , William Robert Tonti
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens , William Robert Tonti
IPC分类号： H01L29/868
CPC分类号： H01L29/868 , H01L29/6609
摘要： Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.
摘要翻译：制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构。一种方法包括：在硅衬底中形成沟槽; 在所述衬底中形成邻接所述沟槽的掺杂区域; 在沟槽的表面上生长本征的外延硅层; 沉积掺杂多晶硅层以填充沟槽中的剩余空间，执行化学机械抛光，使得本征外延硅层和掺杂多晶硅层的顶表面是共面的; 在衬底中形成绝缘隔离层; 在隔离层的顶部形成介电层; 以及通过介电层形成第一金属接触到掺杂多晶硅层，以及通过第二接触到掺杂区域介电层并通过隔离层。

8. 发明申请

US20070284640A1 SEMICONDUCTOR CAPACITORS IN HOT (HYBRID ORIENTATION TECHNOLOGY) SUBSTRATES 失效
标题翻译：半导体电容器（混合方向技术）衬底
公开(公告)号：US20070284640A1
公开(公告)日：2007-12-13
申请号：US11423284
申请日：2006-06-09
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L29/66931
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.
摘要翻译：半导体结构及其形成方法。半导体结构包括半导体衬底。半导体结构还包括在半导体衬底的顶部上的电绝缘区域。半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。半导体结构还包括在绝缘区域的顶部上的第二半导体区域。半导体结构还包括在第一半导体区域和半导体衬底中的电容器。半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。

9. 发明授权

US06727540B2 Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact 有权
标题翻译：制造具有垂直器件阵列和边界位线接触的嵌入式DRAM的结构和方法
公开(公告)号：US06727540B2
公开(公告)日：2004-04-27
申请号：US10227404
申请日：2002-08-23
申请人： Ramachandra Divakaruni , Babar Ali Khan , Carl John Radens
发明人： Ramachandra Divakaruni , Babar Ali Khan , Carl John Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10864
摘要： An integrated circuit including a dynamic random access memory (DRAM) array is disclosed herein in which a DRAM cell includes a storage capacitor within a deep trench, a transistor having a channel extending along a sidewall of the deep trench and a gate conductor within the deep trench, and a wordline contacting the gate conductor from above, wherein the wordline has a centerline which is offset from the centerline of the gate conductor. The DRAM cell further includes active area extending from the transistor channel, and a bitline contact to the active area which is bordered by an insulating spacer of the sidewall of the wordline.
摘要翻译：本文公开了一种包括动态随机存取存储器（DRAM）阵列的集成电路，其中DRAM单元在深沟槽内包括存储电容器，具有沿着深沟槽的侧壁延伸的沟道的晶体管和深沟槽内的栅极导体沟槽和从上方接触栅极导体的字线，其中字线具有偏离栅极导体的中心线的中心线。 DRAM单元进一步包括从晶体管沟道延伸的有源区和与由字线的侧壁的绝缘间隔物界定的有源区的位线接触。

10. 发明申请

US20100173449A1 METHODS OF FABRICATING P-I-N DIODES, STRUCTURES FOR P-I-N DIODES AND DESIGN STRUCTURE FOR P-I-N DIODES 有权
标题翻译：制备P-I-N二极体的方法，P-I-N二极体的结构和P-I-N二极体的设计结构
公开(公告)号：US20100173449A1
公开(公告)日：2010-07-08
申请号：US12349018
申请日：2009-01-06
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens , William Robert Tonti
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens , William Robert Tonti
IPC分类号： H01L31/18 , G06F17/50 , H01L21/02
CPC分类号： H01L29/868 , H01L29/6609
摘要： Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.
摘要翻译：制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构。一种方法包括：在硅衬底中形成沟槽; 在所述衬底中形成邻接所述沟槽的掺杂区域; 在沟槽的表面上生长本征的外延硅层; 沉积掺杂多晶硅层以填充沟槽中的剩余空间，执行化学机械抛光，使得本征外延硅层和掺杂多晶硅层的顶表面是共面的; 在衬底中形成绝缘隔离层; 在隔离层的顶部形成介电层; 以及通过介电层形成第一金属接触到掺杂多晶硅层，以及通过第二接触到掺杂区域介电层并通过隔离层。

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