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1. 发明授权

US06870211B1 Self-aligned array contact for memory cells 失效
标题翻译：用于存储单元的自对准阵列触点
公开(公告)号：US06870211B1
公开(公告)日：2005-03-22
申请号：US10605590
申请日：2003-10-10
申请人： Rama Divakaruni , Johnathan E. Faltermeier , Michael Maldei , Jay Strane
发明人： Rama Divakaruni , Johnathan E. Faltermeier , Michael Maldei , Jay Strane
IPC分类号： H01L21/60 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76897 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897
摘要： A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.
摘要翻译：提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。在槽中形成与基板和位线的位线接触。此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。

2. 发明申请

US20050077562A1 SELF-ALIGNED ARRAY CONTACT FOR MEMORY CELLS 失效
标题翻译：自定义阵列与记忆体的联系
公开(公告)号：US20050077562A1
公开(公告)日：2005-04-14
申请号：US10605590
申请日：2003-10-10
申请人： Rama Divakaruni , Johnathan Faltermeier , Michael Maldei , Jay Strane
发明人： Rama Divakaruni , Johnathan Faltermeier , Michael Maldei , Jay Strane
IPC分类号： H01L21/60 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76897 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897
摘要： A method of forming bitlines for a memory cell array of an integrated circuit and conductive lines interconnecting transistors of an external region outside of the memory cell array is provided. The method includes patterning troughs in a dielectric region covering the memory cell array according to a first critical dimension mask. Bitline contacts to a substrate and bitlines are formed in the troughs. Thereafter, conductive lines are formed which consist essentially of at least one material selected from the group consisting of metals and conductive compounds of metals in horizontally oriented patterns patterned by a second critical dimension mask, wherein the conductive lines interconnect the bitlines to transistors of external circuitry outside of the memory cell array, the conductive lines being interconnected to the bitlines only at peripheral edges of the memory cell array.
摘要翻译：提供一种形成集成电路的存储单元阵列的位线的方法和将存储单元阵列外部的外部区域的晶体管互连的导线。该方法包括根据第一临界尺寸掩模在覆盖存储单元阵列的电介质区域中图形化槽。在槽中形成与基板和位线的位线接触。此后，形成导线，其基本上由选自金属的金属和由第二关键尺寸掩模图案化的水平定向图案中的金属导电化合物组成的组中的至少一种材料组成，其中导线将位线互连到外部电路的晶体管在存储单元阵列外部，导线仅在存储单元阵列的外围边缘处互连到位线。

3. 发明申请

US20050051839A1 REDUCED CAP LAYER EROSION FOR BORDERLESS CONTACTS 失效
标题翻译：减少无边界接触层的层次腐蚀
公开(公告)号：US20050051839A1
公开(公告)日：2005-03-10
申请号：US10655199
申请日：2003-09-04
申请人： Johnathan Faltermeier , Jeremy Stephens , David Dobuzinsky , Larry Clevenger , Munir Naeem , Chienfan Yu , Larry Nesbit , Rama Divakaruni , Michael Maldei
发明人： Johnathan Faltermeier , Jeremy Stephens , David Dobuzinsky , Larry Clevenger , Munir Naeem , Chienfan Yu , Larry Nesbit , Rama Divakaruni , Michael Maldei
IPC分类号： H01L21/60 , H01L21/8242 , H01L29/76
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.
摘要翻译：形成无边界接触的方法和用于半导体器件的无边界接触结构。优选实施例包括使用设置在第一蚀刻选择性材料上的第二蚀刻选择性材料，以在半导体器件的各种材料层的蚀刻工艺期间保持第一蚀刻选择性材料，同时形成无边界接触。

4. 发明授权

US06890815B2 Reduced cap layer erosion for borderless contacts 失效
标题翻译：减少无边界接触的盖层侵蚀
公开(公告)号：US06890815B2
公开(公告)日：2005-05-10
申请号：US10655199
申请日：2003-09-04
申请人： Johnathan Faltermeier , Jeremy Stephens , David Dobuzinsky , Larry Clevenger , Munir D. Naeem , Chienfan Yu , Larry Nesbit , Rama Divakaruni , Michael Maldei
发明人： Johnathan Faltermeier , Jeremy Stephens , David Dobuzinsky , Larry Clevenger , Munir D. Naeem , Chienfan Yu , Larry Nesbit , Rama Divakaruni , Michael Maldei
IPC分类号： H01L21/60 , H01L21/8242 , H01L29/76
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10864 , H01L27/10876 , H01L27/10891
摘要： A method of forming borderless contacts and a borderless contact structure for semiconductor devices. A preferred embodiment comprises using a second etch selectivity material disposed over a first etch selectivity material to preserve the first etch selectivity material during the etch processes for the various material layers of the semiconductor device while forming the borderless contacts.
摘要翻译：形成无边界接触的方法和用于半导体器件的无边界接触结构。优选实施例包括使用设置在第一蚀刻选择性材料上的第二蚀刻选择性材料，以在半导体器件的各种材料层的蚀刻工艺期间保持第一蚀刻选择性材料，同时形成无边界接触。

5. 发明授权

US07163864B1 Method of fabricating semiconductor side wall fin 有权
标题翻译：制造半导体侧壁翅片的方法
公开(公告)号：US07163864B1
公开(公告)日：2007-01-16
申请号：US09691353
申请日：2000-10-18
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.
摘要翻译：通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

6. 发明授权

US07030481B2 High density chip carrier with integrated passive devices 有权
标题翻译：具有集成无源器件的高密度芯片载体
公开(公告)号：US07030481B2
公开(公告)日：2006-04-18
申请号：US10314589
申请日：2002-12-09
申请人： Michael Patrick Chudzik , Robert H. Dennard , Rama Divakaruni , Bruce Kenneth Furman , Rajarao Jammy , Chandrasekhar Narayan , Sampath Purushothaman , Joseph F. Shepard, Jr. , Anna Wanda Topol
发明人： Michael Patrick Chudzik , Robert H. Dennard , Rama Divakaruni , Bruce Kenneth Furman , Rajarao Jammy , Chandrasekhar Narayan , Sampath Purushothaman , Joseph F. Shepard, Jr. , Anna Wanda Topol
IPC分类号： H01L23/053
CPC分类号： H05K1/162 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/50 , H01L2224/16225 , H01L2924/01019 , H01L2924/01055 , H01L2924/01077 , H01L2924/01078 , H01L2924/15311 , H01L2924/157 , H01L2924/30105 , H05K1/167 , H05K3/4602 , H05K2201/09809
摘要： A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.
摘要翻译：提供了一种用于半导体部件的载体，其具有集成在其基板中的无源部件。无源组件包括去耦组件，例如电容器和电阻器。一组连接被集成以提供与受支持的部件的紧密的电气接近。

7. 发明授权

US06998666B2 Nitrided STI liner oxide for reduced corner device impact on vertical device performance 有权
标题翻译：氮化氮化物衬垫氧化物，用于减少拐角装置对垂直装置性能的影响
公开(公告)号：US06998666B2
公开(公告)日：2006-02-14
申请号：US10707754
申请日：2004-01-09
申请人： Jochen Beintner , Rama Divakaruni , Rajarao Jammy
发明人： Jochen Beintner , Rama Divakaruni , Rajarao Jammy
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10894
摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.
摘要翻译：一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极导体和掺硼通道。该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。然后在DRAM单元的两侧的沟槽中形成隔离区。此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。

8. 发明申请

US20050184359A1 STRUCTURE AND METHOD OF SELF-ALIGNED BIPOLAR TRANSISTOR HAVING TAPERED COLLECTOR 有权
标题翻译：带有收集器的自对准双极晶体管的结构和方法
公开(公告)号：US20050184359A1
公开(公告)日：2005-08-25
申请号：US10708340
申请日：2004-02-25
申请人： Hiroyuki Akatsu , Rama Divakaruni , Gregory Freeman , David Greenberg , Marwan Khater , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Gregory Freeman , David Greenberg , Marwan Khater , William Tonti
IPC分类号： H01L21/331 , H01L27/082 , H01L29/08 , H01L29/737
CPC分类号： H01L29/66242 , H01L29/0821 , H01L29/7378
摘要： A bipolar transistor is provided which includes a tapered, i.e. frustum-shaped, collector pedestal having an upper substantially planar surface, a lower surface, and a slanted sidewall extending between the upper surface and the lower surface, the upper surface having substantially less area than the lower surface. The bipolar transistor further includes an intrinsic base overlying the upper surface of the collector pedestal, a raised extrinsic base conductively connected to the intrinsic base and an emitter overlying the intrinsic base. In a particular embodiment, the emitter is self-aligned to the collector pedestal, having a centerline which is aligned to the centerline of the collector pedestal.
摘要翻译：提供了一种双极晶体管，其包括锥形的，即截头锥形的收集器基座，其具有上部基本平坦的表面，下表面和在上表面和下表面之间延伸的倾斜侧壁，上表面具有基本上较小的面积下表面。双极晶体管还包括覆盖集电极基座的上表面的本征基极，与本征基极导电连接的升高的外部基极和覆盖本征基极的发射极。在特定实施例中，发射器与收集器基座自对准，具有与收集器基座的中心线对准的中心线。

9. 发明授权

US06869860B2 Filling high aspect ratio isolation structures with polysilazane based material 失效
标题翻译：用聚硅氮烷基材料填充高纵横比隔离结构
公开(公告)号：US06869860B2
公开(公告)日：2005-03-22
申请号：US10250092
申请日：2003-06-03
申请人： Michael P. Belyansky , Rama Divakaruni , Laertis Economikos , Rajarao Jammy , Kenneth T. Settlemeyer, Jr. , Padraic C. Shafer
发明人： Michael P. Belyansky , Rama Divakaruni , Laertis Economikos , Rajarao Jammy , Kenneth T. Settlemeyer, Jr. , Padraic C. Shafer
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76229
摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.
摘要翻译：包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率通过HDP技术，并且耐用性足以承受CMP抛光。

10. 发明授权

US06762447B1 Field-shield-trench isolation for gigabit DRAMs 有权
标题翻译：用于千兆位DRAM的场屏蔽沟槽隔离
公开(公告)号：US06762447B1
公开(公告)日：2004-07-13
申请号：US09245269
申请日：1999-02-05
申请人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
发明人： Jack A. Mandelman , Rama Divakaruni , Giuseppe Larosa , Ulrike Gruening , Carl Radens
IPC分类号： H01L27108
CPC分类号： H01L27/10861 , H01L21/763 , H01L21/765 , H01L27/10829 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： A dynamic random access memory (DRAM) formed in a semiconductor body has individual pairs of memory cells that are isolated from one another by a vertical electrical isolation trench and are isolated from support circuitry. The isolation trench has sidewalls and upper and lower portions, and encircles an area of the semiconductor body which contains the memory cells. This electrically isolates pairs of memory cells from each other and from the support circuitry contained within the semiconductor body but not located within the encircled area. The lower portion of the isolation trench is filled with an electrically conductive material that has sidewall portions thereof which are at least partly separated from the sidewalls of the lower portion of the trench by a first electrical insulator, and that has a lower portion that is in electrical contact with the semiconductor body. The upper portion of the isolation trench is filled with a second electrical insulator.
摘要翻译：形成在半导体主体中的动态随机存取存储器（DRAM）具有通过垂直电隔离沟槽彼此隔离并且与支持电路隔离的各对存储单元。隔离沟槽具有侧壁和上部和下部，并且包围包含存储单元的半导体主体的区域。这使得存储器单元对彼此和从包含在半导体本体内但不位于包围区域内的支撑电路电隔离。隔离沟槽的下部填充有导电材料，该导电材料具有其侧壁部分，其侧壁部分通过第一电绝缘体至少部分地与沟槽的下部的侧壁分离，并且其具有位于与半导体本体电接触。隔离沟槽的上部填充有第二电绝缘体。

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