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1. 发明授权

US07361556B2 Method of fabricating semiconductor side wall fin 有权
标题翻译：制造半导体侧壁翅片的方法
公开(公告)号：US07361556B2
公开(公告)日：2008-04-22
申请号：US11495518
申请日：2006-07-31
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.
摘要翻译：通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

2. 发明授权

US07265417B2 Method of fabricating semiconductor side wall fin 有权
公开(公告)号：US07265417B2
公开(公告)日：2007-09-04
申请号：US10867772
申请日：2004-06-16
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L27/01
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

3. 发明授权

US07163864B1 Method of fabricating semiconductor side wall fin 有权
标题翻译：制造半导体侧壁翅片的方法
公开(公告)号：US07163864B1
公开(公告)日：2007-01-16
申请号：US09691353
申请日：2000-10-18
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66484 , H01L29/66795 , H01L29/78654 , H01L29/78687
摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.
摘要翻译：通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

4. 发明授权

US06472258B1 Double gate trench transistor 失效
标题翻译：双栅沟槽晶体管
公开(公告)号：US06472258B1
公开(公告)日：2002-10-29
申请号：US09711725
申请日：2000-11-13
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Jed H. Rankin
IPC分类号： H01L2130
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66818
摘要： A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.
摘要翻译：场效应晶体管由亚光刻导电沟道和双栅极形成，该双栅极通过简单的工艺由绝缘体上硅晶片开始形成，允许大多数蚀刻工艺使用掩埋氧化物作为蚀刻停止。通过硅化物侧壁或衬垫实现栅极，源极和漏极的低电阻率，而通过从源极和漏极区域边缘凹陷硅化物和多晶硅双栅极结构来实现低栅极至结电容。

5. 发明授权

US07112845B2 Double gate trench transistor 失效
公开(公告)号：US07112845B2
公开(公告)日：2006-09-26
申请号：US10064171
申请日：2002-06-18
申请人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Jed H. Rankin
发明人： James W. Adkisson , Paul D. Agnello , Arne W. Ballantine , Rama Divakaruni , Erin C. Jones , Jed H. Rankin
IPC分类号： H01L27/01
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/4908 , H01L29/66818
摘要： A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

6. 发明授权

US06406962B1 Vertical trench-formed dual-gate FET device structure and method for creation 失效
标题翻译：垂直沟槽形双栅FET器件结构及其制作方法
公开(公告)号：US06406962B1
公开(公告)日：2002-06-18
申请号：US09761931
申请日：2001-01-17
申请人： Paul D. Agnello , Arne W. Ballantine , Ramachandra Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
发明人： Paul D. Agnello , Arne W. Ballantine , Ramachandra Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21336
CPC分类号： H01L29/78648 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/78642
摘要： The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.
摘要翻译：本发明涉及一种形成具有垂直沟槽形成的双栅极的一个或多个FET的装置和方法，其中多个氮化物层具有周期性地设置在其上的氧化物标记蚀刻停止层，从而使FET具有多个可选择的栅极长度。本发明提供控制和形成尺寸缩小到约5nm至约100nm，优选约5nm至约50nm的栅极长度。具有氧化物蚀刻停止层的多个衬垫氮化物层通过蚀刻衬垫氮化物层中的多个通孔来提供本FET连接到具有对应于所使用的栅极长度的各种连接深度的多个触点由此这些通孔在选定的蚀刻停止层处停止以提供适于与所选择的这些触点连接的通孔。附加的栅极材料可以沉积在所选择的多个氮化物层的顶表面上，以允许与任何给定FET的栅电极的接触。

7. 发明授权

US06448590B1 Multiple threshold voltage FET using multiple work-function gate materials 失效
标题翻译：多阈值电压FET采用多功能栅极材料
公开(公告)号：US06448590B1
公开(公告)日：2002-09-10
申请号：US09695199
申请日：2000-10-24
申请人： James W. Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
发明人： James W. Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
IPC分类号： H01L2710
CPC分类号： H01L29/4916 , H01L21/82345 , H01L29/4238 , H01L29/495 , H01L29/4966 , H01L29/66666 , H01L29/7827
摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.
摘要翻译：通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。通过组合多个功能门极材料来开发多个阈值电压。栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。开发了用于多阈值电压设计的图案化线性阵列实施例。形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。栅极材料被布置成彼此靠近以适应小栅极长度设计。

8. 发明授权

US06797553B2 Method for making multiple threshold voltage FET using multiple work-function gate materials 有权
标题翻译：使用多功能栅极材料制造多个阈值电压FET的方法
公开(公告)号：US06797553B2
公开(公告)日：2004-09-28
申请号：US10205143
申请日：2002-07-24
申请人： James W Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
发明人： James W Adkisson , Arne W. Ballantine , Ramachandra Divakaruni , Jeffrey B. Johnson , Erin C. Jones , Hon-Sum P. Wong
IPC分类号： H01L218238
CPC分类号： H01L29/4916 , H01L21/82345 , H01L29/4238 , H01L29/495 , H01L29/4966 , H01L29/66666 , H01L29/7827
摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.
摘要翻译：通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。通过组合多个功能门极材料来开发多个阈值电压。栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。开发了用于多阈值电压设计的图案化线性阵列实施例。形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。栅极材料被布置成彼此靠近以适应小栅极长度设计。

9. 发明申请

US20080227270A1 LOW TEMPERATURE FUSION BONDING WITH HIGH SURFACE ENERGY USING A WET CHEMICAL TREATMENT 失效
标题翻译：使用湿式化学处理的高温表面能量的低温熔融粘结
公开(公告)号：US20080227270A1
公开(公告)日：2008-09-18
申请号：US12128259
申请日：2008-05-28
申请人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra , Leathen Shi , Dinkar V. Singh
发明人： Kevin K. Chan , Kathryn Wilder Guarini , Erin C. Jones , Antonio F. Saavedra , Leathen Shi , Dinkar V. Singh
IPC分类号： H01L21/46
CPC分类号： H01L21/02052 , H01L21/02164 , H01L21/02343 , H01L21/2007 , H01L21/306 , H01L21/3105 , H01L21/31612 , H01L21/31662 , H01L21/76251
摘要： Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.
摘要翻译：描述了涉及NH 4 OH的湿化学表面处理，其能够使诸如半导体（例如Si）的两个晶片与绝缘体（例如，SiO 2）的极强直接接合，在低温（小于或等于400℃）。使用这些表面处理中的一些已经实现了键合界面的高达〜4835±675mJ / m 2的表面能。该值与报告的显着更高的处理温度（小于1000℃）的值相当。本文还可以实现具有优异产率和约2500mJ / m 2的表面能的无空隙键合界面。

10. 发明授权

US06762101B2 Damascene double-gate FET 有权
标题翻译：大马士革双栅FET
公开(公告)号：US06762101B2
公开(公告)日：2004-07-13
申请号：US10411727
申请日：2003-04-11
申请人： Kevin K. Chan , Erin C. Jones , Paul M. Solomon , Hon-Sum Phillip Wong
发明人： Kevin K. Chan , Erin C. Jones , Paul M. Solomon , Hon-Sum Phillip Wong
IPC分类号： H01L21336
CPC分类号： H01L29/66772 , H01L29/4908 , H01L29/78648
摘要： A double-gate field effect transistor (DGFET) is provided using a damascene-like replacement gate processing step to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench. The damascene-like replacement gate processing step allows for the fabrication of a tapered transistor body region having a thicker body under the contacts which reduces access resistance.
摘要翻译：使用大马士革式替代栅极处理步骤提供双栅极场效应晶体管（DGFET），以在先前形成的沟槽内部产生侧壁源极/漏极区域，氧化物间隔物和栅极结构。大马士革式的替代栅极处理步骤允许制造在触点下方具有较厚主体的锥形晶体管主体区域，从而降低访问阻力。

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