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1. 发明授权

US08595554B2 Reproducibility in a multiprocessor system 有权
标题翻译：多处理器系统中的重现性
公开(公告)号：US08595554B2
公开(公告)日：2013-11-26
申请号：US12774475
申请日：2010-05-05
申请人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F11/00
CPC分类号： G06F1/10 , G06F11/2242
摘要： Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
摘要翻译：如果问题是可重现的，通常会大大帮助解决问题。为了确保多处理器系统的可重复性，提出了以下方面：确定性系统启动状态，单个系统时钟，系统中的时钟相位对齐，全系统同步事件，系统组件的可重复执行，确定性芯片接口，零 - 与系统进行通信，精确地停止系统并扫描系统状态。

2. 发明申请

US20110119521A1 REPRODUCIBILITY IN A MULTIPROCESSOR SYSTEM 有权
标题翻译：多处理器系统中的可重复性
公开(公告)号：US20110119521A1
公开(公告)日：2011-05-19
申请号：US12774475
申请日：2010-05-05
申请人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
发明人： Ralph A. Bellofatto , Dong Chen , Paul W. Coteus , Noel A. Eisley , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Philip Heidelberger , Gerard V. Kopcsay , Thomas A. Liebsch , Martin Ohmacht , Don D. Reed , Robert M. Senger , Burkhard Steinmacher-Burow , Yutaka Sugawara
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , G06F11/2242
摘要： Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
摘要翻译：如果问题是可重现的，通常会大大帮助解决问题。为了确保多处理器系统的可重复性，提出了以下方面：确定性系统启动状态，单个系统时钟，系统中的时钟相位对齐，全系统同步事件，系统组件的可重复执行，确定性芯片接口，零 - 与系统进行通信，精确地停止系统并扫描系统状态。

3. 发明授权

US08412974B2 Global synchronization of parallel processors using clock pulse width modulation 有权
标题翻译：使用时钟脉宽调制的并行处理器的全局同步
公开(公告)号：US08412974B2
公开(公告)日：2013-04-02
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/04 , G06F1/12 , G06F15/16
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

4. 发明申请

US20110119475A1 GLOBAL SYNCHRONIZATION OF PARALLEL PROCESSORS USING CLOCK PULSE WIDTH MODULATION 有权
标题翻译：使用时钟脉冲宽度调制的并行处理器的全局同步
公开(公告)号：US20110119475A1
公开(公告)日：2011-05-19
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/12 , G06F1/10 , G06F9/00 , G06F1/08
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

5. 发明申请

US20120266008A1 SYSTEM-WIDE POWER MANAGEMENT CONTROL VIA CLOCK DISTRIBUTION NETWORK 有权
标题翻译：通过时钟分配网络进行系统的电源管理控制
公开(公告)号：US20120266008A1
公开(公告)日：2012-10-18
申请号：US13085879
申请日：2011-04-13
申请人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
发明人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
IPC分类号： G06F1/12
CPC分类号： G06F1/329 , G06F1/10 , G06F1/12 , G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D10/24
摘要： An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
摘要翻译：一种用于自动控制包括多个处理器的并行计算系统的功耗的装置，方法和计算机程序产品。计算设备向并行计算系统发出命令。时钟脉冲宽度调制器对系统时钟信号中的命令进行编码，以分配给多个处理器。并行计算系统中的多个处理器接收包括编码命令的系统时钟信号，并根据编码命令调整功耗。

6. 发明授权

US09037892B2 System-wide power management control via clock distribution network 有权
标题翻译：通过时钟分配网络进行全系统的电源管理控制
公开(公告)号：US09037892B2
公开(公告)日：2015-05-19
申请号：US13085879
申请日：2011-04-13
申请人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
发明人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
IPC分类号： G06F1/04 , G06F1/12 , G06F1/32 , G06F1/10 , G06F1/20
CPC分类号： G06F1/329 , G06F1/10 , G06F1/12 , G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D10/24
摘要： An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
摘要翻译：一种用于自动控制包括多个处理器的并行计算系统的功耗的装置，方法和计算机程序产品。计算设备向并行计算系统发出命令。时钟脉冲宽度调制器对系统时钟信号中的命令进行编码，以分配给多个处理器。并行计算系统中的多个处理器接收包括编码命令的系统时钟信号，并根据编码命令调整功耗。

7. 发明授权

US07941681B2 Proactive power management in a parallel computer 有权
标题翻译：并行计算机中的主动电源管理
公开(公告)号：US07941681B2
公开(公告)日：2011-05-10
申请号：US11840711
申请日：2007-08-17
申请人： Thomas M. Gooding , Todd A. Inglett , Thomas A. Liebsch , Thomas E. Musta , Don D. Reed
发明人： Thomas M. Gooding , Todd A. Inglett , Thomas A. Liebsch , Thomas E. Musta , Don D. Reed
IPC分类号： G06F1/32
CPC分类号： G06F9/4843 , G06F1/3203 , G06F1/329 , Y02D10/24
摘要： Proactive power management in a parallel computer, the parallel computer including a service node and a plurality of compute nodes, the service node connected to the compute nodes through an out-of-band service network, each compute node including a computer processor and a computer memory operatively coupled to the computer processor. Embodiments include receiving, by the service node, a user instruction to initiate a job on an operational group of compute nodes in the parallel computer, the instruction including power management attributes for the compute nodes; setting, by the service node in accordance with the power management attributes for the compute nodes of the operational group, power consumption ratios for each compute node of the operational group including a computer processor power consumption ratio and a computer memory power consumption ratio; and initiating, by the service node, the job on the compute nodes of the operational group of the parallel computer.
摘要翻译：并行计算机中的主动功率管理，并行计算机包括服务节点和多个计算节点，服务节点通过带外服务网络连接到计算节点，每个计算节点包括计算机处理器和计算机可操作地耦合到计算机处理器的存储器。实施例包括由服务节点接收用于在并行计算机中的计算节点的操作组上发起作业的用户指令，所述指令包括用于计算节点的功率管理属性; 由服务节点根据操作组的计算节点的功率管理属性设置包括计算机处理器功耗比和计算机存储器功耗比的操作组的每个计算节点的功耗比; 并且由服务节点发起并行计算机的操作组的计算节点上的作业。

8. 发明申请

US20090049313A1 Proactive Power Management in a Parallel Computer 有权
标题翻译：并行计算机中的主动电源管理
公开(公告)号：US20090049313A1
公开(公告)日：2009-02-19
申请号：US11840711
申请日：2007-08-17
申请人： Thomas M Gooding , Todd A. Inglett , Thomas A. Liebsch , Thomas E. Musta , Don D. Reed
发明人： Thomas M Gooding , Todd A. Inglett , Thomas A. Liebsch , Thomas E. Musta , Don D. Reed
IPC分类号： G06F1/00
CPC分类号： G06F9/4843 , G06F1/3203 , G06F1/329 , Y02D10/24
摘要： Proactive power management in a parallel computer, the parallel computer including a service node and a plurality of compute nodes, the service node connected to the compute nodes through an out-of-band service network, each compute node including a computer processor and a computer memory operatively coupled to the computer processor. Embodiments include receiving, by the service node, a user instruction to initiate a job on an operational group of compute nodes in the parallel computer, the instruction including power management attributes for the compute nodes; setting, by the service node in accordance with the power management attributes for the compute nodes of the operational group, power consumption ratios for each compute node of the operational group including a computer processor power consumption ratio and a computer memory power consumption ratio; and initiating, by the service node, the job on the compute nodes of the operational group of the parallel computer.
摘要翻译：并行计算机中的主动功率管理，并行计算机包括服务节点和多个计算节点，服务节点通过带外服务网络连接到计算节点，每个计算节点包括计算机处理器和计算机可操作地耦合到计算机处理器的存储器。实施例包括由服务节点接收用于在并行计算机中的计算节点的操作组上发起作业的用户指令，所述指令包括用于计算节点的功率管理属性; 由服务节点根据操作组的计算节点的功率管理属性设置包括计算机处理器功耗比和计算机存储器功耗比的操作组的每个计算节点的功耗比; 并且由服务节点发起并行计算机的操作组的计算节点上的作业。

9. 发明授权

US07877620B2 Managing power in a parallel computer 有权
标题翻译：在并行计算机中管理电源
公开(公告)号：US07877620B2
公开(公告)日：2011-01-25
申请号：US11840743
申请日：2007-08-17
申请人： Alan Gara , Thomas M. Gooding , Todd A. Inglett , Thomas A. Liebsch , Thomas E. Musta
发明人： Alan Gara , Thomas M. Gooding , Todd A. Inglett , Thomas A. Liebsch , Thomas E. Musta
IPC分类号： G06F1/26
CPC分类号： G06F1/263 , G06F1/3203
摘要： Managing power in a parallel computer, the parallel computer including a power supply and a plurality of compute nodes, the plurality of compute nodes powered by the power supply through a plurality of DC-DC converters, each DC-DC converter supplying current to an assigned group of compute nodes, each DC-DC converter having a current sensor. Embodiments include monitoring, by the current sensor, an amount of current supplied by that DC-DC converter to its assigned group of compute nodes; determining, by at least one DC-DC converter, that the amount of current supplied is greater than a predefined threshold value; sending, by the at least one DC-DC converter to the plurality of compute nodes, a global interrupt, including notifying the plurality of compute nodes to reduce power consumption; and reducing, by the plurality of compute nodes in accordance with power consumption ratios, power consumption of the compute nodes.
摘要翻译：在并行计算机中管理并行计算机，并行计算机包括电源和多个计算节点，所述多个计算节点由电源通过多个DC-DC转换器供电，每个DC-DC转换器将电流提供给所分配的一组计算节点，每个DC-DC转换器具有电流传感器。实施例包括由电流传感器监测由该DC-DC转换器提供给其分配的计算节点组的电流量; 由至少一个DC-DC转换器确定所提供的电流量大于预定阈值; 由所述至少一个DC-DC转换器向所述多个计算节点发送全局中断，包括通知所述多个计算节点以减少功耗; 并且根据功耗比由所述多个计算节点减少所述计算节点的功率消耗。

10. 发明申请

US20090049317A1 Managing Power in a Parallel Computer 有权
标题翻译：在并行计算机中管理电源
公开(公告)号：US20090049317A1
公开(公告)日：2009-02-19
申请号：US11840743
申请日：2007-08-17
申请人： Alan Gara , Thomas M. Gooding , Todd A. Inglett , Thomas A. Liebsch , Thomas E. Musta
发明人： Alan Gara , Thomas M. Gooding , Todd A. Inglett , Thomas A. Liebsch , Thomas E. Musta
IPC分类号： G06F1/32
CPC分类号： G06F1/263 , G06F1/3203
摘要： Managing power in a parallel computer, the parallel computer including a power supply and a plurality of compute nodes, the plurality of compute nodes powered by the power supply through a plurality of DC-DC converters, each DC-DC converter supplying current to an assigned group of compute nodes, each DC-DC converter having a current sensor. Embodiments include monitoring, by the current sensor, an amount of current supplied by that DC-DC converter to its assigned group of compute nodes; determining, by at least one DC-DC converter, that the amount of current supplied is greater than a predefined threshold value; sending, by the at least one DC-DC converter to the plurality of compute nodes, a global interrupt, including notifying the plurality of compute nodes to reduce power consumption; and reducing, by the plurality of compute nodes in accordance with power consumption ratios, power consumption of the compute nodes.
摘要翻译：在并行计算机中管理并行计算机，并行计算机包括电源和多个计算节点，所述多个计算节点由电源通过多个DC-DC转换器供电，每个DC-DC转换器将电流提供给所分配的一组计算节点，每个DC-DC转换器具有电流传感器。实施例包括由电流传感器监测由该DC-DC转换器提供给其分配的计算节点组的电流量; 由至少一个DC-DC转换器确定所提供的电流量大于预定阈值; 由所述至少一个DC-DC转换器向所述多个计算节点发送全局中断，包括通知所述多个计算节点以减少功耗; 并且根据功耗比由所述多个计算节点减少所述计算节点的功率消耗。

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