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    • 1. 发明授权
    • Trench capacitors with reduced polysilicon stress
    • 减少多晶硅应力的沟槽电容器
    • US06872620B2
    • 2005-03-29
    • US10441887
    • 2003-05-20
    • Dureseti ChidambarraoRajarao JammyJack A. Mandelman
    • Dureseti ChidambarraoRajarao JammyJack A. Mandelman
    • H01L21/8242H01L21/20
    • H01L27/10867
    • A Deep Trench (DT) capacitor in a semiconductor substrate has an isolation collar formed on trench sidewalls above the DT bottom. An outer plate is formed below the collar. Capacitor dielectric is formed on DT walls below the collar. An node electrode is formed in the DT, recessed below the DT top. The collar is recessed in the DT. A combined poly/counter-recrystallizing species cap is formed over the node electrode with a peripheral strap. The cap may be formed after formed a peripheral divot of a recessed collar, followed by forming an intrinsic poly strap in the divot and doping with a counter-recrystallization species, e.g. Ge, into the node electrode and the strap. Alternatively, the node electrode is recessed followed by codeposition of poly and Ge or another counter-recrystallization species to form the cap and strap.
    • 半导体衬底中的深沟槽(DT)电容器具有形成在DT底部上方的沟槽侧壁上的隔离环。 在轴环下形成一个外板。 电容电介质形成在轴环下面的DT壁上。 节点电极形成在DT上,凹陷在DT顶部下方。 衣领凹入DT。 在具有外围带的节点电极上形成组合的聚/反重结晶物质盖。 可以在形成凹陷环的外围边缘之后形成盖,然后在该凹陷中形成本征多晶带并掺杂反相再结晶物质,例如, Ge,进入节点电极和带子。 或者,节点电极凹进,随后聚合和Ge的共沉积或另一种反重结晶物质形成盖和带。
    • 10. 发明授权
    • DRAM trench
    • DRAM沟槽
    • US06222218B1
    • 2001-04-24
    • US09152835
    • 1998-09-14
    • Rajarao JammyJack A. MandelmanCarl J. Radens
    • Rajarao JammyJack A. MandelmanCarl J. Radens
    • H01L27108
    • H01L27/10861
    • The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor. Specifically, the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing. This process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material. Furthermore, the process of the present invention limits the extent of the buried-strap outdiffusion, thus improving the electrical characteristics of the array MOSFET.
    • 本发明涉及制造半导体存储器结构,特别是深沟槽半导体存储器件的工艺,其中将温度敏感的高介电常数材料并入电容器的存储节点中。 具体地,本发明描述了在高温浅沟槽隔离和栅极导体处理之后形成深沟槽存储电容器的工艺。 该过程允许将温度敏感的高介电常数材料并入电容器结构中而不会导致该材料的分解。 此外,本发明的方法限制了埋层扩散的程度,从而改善阵列MOSFET的电特性。