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    • 3. 发明授权
    • Semiconductor testing device with redundant circuits
    • 具有冗余电路的半导体测试装置
    • US5994914A
    • 1999-11-30
    • US900339
    • 1997-07-25
    • Hiromi Tsuruta
    • Hiromi Tsuruta
    • H01L21/66G01R31/311H01L21/82H01L21/822H01L27/04G01R31/28
    • G01R31/311
    • In a semiconductor testing device, the defective data of a semiconductor device which is detected by a defective detection unit 1 are converted to address data on the basis of inherent information such as the cell size, the divisional size, etc. of the semiconductor device by an address conversion unit 2, and the address data are compared with a redundant circuit area of the semiconductor device to make a quality (defective or non-defective) judgment of the semiconductor device by a judgment unit 3, whereby when any defective exists in the semiconductor device, the judgment as to whether the defective is replaceable (relievable) by the redundant circuits can be more accurately performed.
    • 在半导体测试装置中,由缺陷检测单元1检测到的半导体器件的缺陷数据根据诸如半导体器件的单元尺寸,分区尺寸等的固有信息被转换为地址数据, 地址转换单元2和地址数据与半导体器件的冗余电路区域进行比较,以通过判断单元3进行半导体器件的质量(有缺陷或无缺陷)判断,从而当存在缺陷存在于 可以更准确地执行关于该冗余电路是否可替换(可解除)故障的判断。