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1. 发明申请

WO2011041064A2 METHODS AND SYSTEMS FOR REDUCING SUPPLY AND TERMINATION NOISE 审中-公开
标题翻译：减少供应和终止噪声的方法和系统
公开(公告)号：WO2011041064A2
公开(公告)日：2011-04-07
申请号：PCT/US2010/047466
申请日：2010-09-01
申请人： RAMBUS INC. , OH, Kyung, Suk
发明人： OH, Kyung, Suk
IPC分类号： G11C7/10
CPC分类号： H03K19/0005 , G11C5/063 , G11C7/02 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2207/2254
摘要： Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction.
摘要翻译：描述的是第一集成电路（IC）中的通信系统通过单端通信信道与第二IC进行通信。双向参考通道在第一和第二IC之间延伸并在两端终止。参考通道每端的终端阻抗支持用于在不同方向上传送信号的不同模式。可以针对每个信令方向优化参考信道的终止阻抗。

2. 发明申请

WO2010147608A1 FREQUENCY RESPONSIVE BUS CODING 审中-公开
标题翻译：频率响应总线编码
公开(公告)号：WO2010147608A1
公开(公告)日：2010-12-23
申请号：PCT/US2009/066253
申请日：2009-12-01
申请人： RAMBUS, INC. , OH, Kyung, Suk , WILSON, John , KIM, Joong-Ho , REN, Jihong
发明人： OH, Kyung, Suk , WILSON, John , KIM, Joong-Ho , REN, Jihong
IPC分类号： G06F13/38 , G06F13/40 , G06F9/00
CPC分类号： H04L25/49 , H04L25/4915
摘要： A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels ("DBI_DC") and a measure of a number of logic level transitions relative to a prior signal ("DBI_AC") provides a measure of control that may be used to compensate for both main and predriver switching noise.
摘要翻译：数据系统允许基于总线的频率和总线上的切换频率的总线编码，以避免不期望的频率条件，例如谐振条件或与其他电气设备的干扰。监视一个或多个总线的传输频率并用于控制编码过程，例如，基于数据总线反转（DBI）的编码处理。使用绝对数量逻辑电平（“DBI_DC”）的度量和相对于先前信号（“DBI_AC”）的逻辑电平转换的数量的度量提供了可用于补偿主要和预先切换的开关噪声。

3. 发明申请

WO2011159465A2 BALANCED ON-DIE TERMINATION 审中-公开
标题翻译：平衡点对点终止
公开(公告)号：WO2011159465A2
公开(公告)日：2011-12-22
申请号：PCT/US2011/038656
申请日：2011-06-01
申请人： RAMBUS INC. , WILSON, John , KIM, Joong-Ho , KOLLIPARA, Ravindranath , SECKER, David , OH, Kyung, Suk
发明人： WILSON, John , KIM, Joong-Ho , KOLLIPARA, Ravindranath , SECKER, David , OH, Kyung, Suk
IPC分类号： G11C7/10
CPC分类号： G06F13/4086 , G06F13/4234
摘要： Termination of a high-speed signaling link is effected by simultaneously engaging on- die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.
摘要翻译：高速信令链路的终止通过同时接合设置在同一存储器模块上的多个集成电路存储器件中和/或在相同的集成电路封装内的管芯端接结构来实现，并且耦合到高速信号链路信令链路。

4. 发明申请

WO2012118714A3 TIMING CALIBRATION FOR MULTIMODE I/O SYSTEMS 审中-公开
公开(公告)号：WO2012118714A3
公开(公告)日：2012-09-07
申请号：PCT/US2012/026583
申请日：2012-02-24
申请人： RAMBUS INC. , OH, Kyung, Suk , BANSAL, Akash
发明人： OH, Kyung, Suk , BANSAL, Akash
IPC分类号： G06F13/38 , G06F13/14 , G11C7/10 , G11C7/22
摘要： Integrated circuit devices that operate in different modes. In a low data rate mode, data is transferred between the integrated circuit devices at a low data rate, or no data is transferred at all. In a high data rate mode, data is transferred between integrated circuit devices at a high data rate. A transition mode facilitates the transition from the low data rate mode to the high data rate mode. During the transition mode data is transferred between the integrated circuit devices at an intermediate data rate greater than the low data rate but lower than the high data rate. Also during the transition mode, parameters affecting the transmission of data between the integrated circuit devices are calibrated at the high data rate.

5. 发明申请

WO2008085299A1 RECEIVER WITH CLOCK RECOVERY CIRCUIT AND ADAPTIVE SAMPLE AND EQUALIZER TIMING 审中-公开
标题翻译：采用时钟恢复电路和自适应采样和均衡时序
公开(公告)号：WO2008085299A1
公开(公告)日：2008-07-17
申请号：PCT/US2007/025634
申请日：2007-12-13
申请人： RAMBUS INC. , LIN, Qi , LEIBOWITZ, Brian , LEE, Hae-chang , REN, Jihong , OH, Kyung, Suk , ZERBE, Jared
发明人： LIN, Qi , LEIBOWITZ, Brian , LEE, Hae-chang , REN, Jihong , OH, Kyung, Suk , ZERBE, Jared
IPC分类号： H04L7/02 , H04L7/00 , H04L25/03
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter- symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
摘要翻译：接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。采样和均衡器定时被转移到具有相对于当前符号的残余符号间干扰（ISI）能量较少的位置。可以使用信号质量的测量（诸如接收机比特错误率或滤波器抽头值的比较）来计算移位的位置，以优化数据恢复的定时。

6. 发明公开

EP2443558A1 FREQUENCY RESPONSIVE BUS CODING 有权转让
标题翻译：频率响应总线编码
公开(公告)号：EP2443558A1
公开(公告)日：2012-04-25
申请号：EP09846307.8
申请日：2009-12-01
申请人： Rambus Inc.
发明人： OH, Kyung, Suk , WILSON, John , KIM, Joong-Ho , REN, Jihong
IPC分类号： G06F13/38 , G06F13/40 , G06F9/00
CPC分类号： H04L25/49 , H04L25/4915
摘要： A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels ("DBI_DC") and a measure of a number of logic level transitions relative to a prior signal ("DBI_AC") provides a measure of control that may be used to compensate for both main and predriver switching noise.
摘要翻译：数据系统允许基于总线的频率和总线上的开关频率进行总线编码，从而避免不希望的频率条件，例如谐振条件或与其他电气设备的干扰。沿着一个或多个总线的传输频率被监控并用于控制编码过程，例如，基于数据总线反转（DBI）的编码过程。使用绝对数量的逻辑电平（“DBI_DC”）的度量和相对于先前信号（“DBI_AC”）的多个逻辑电平转换的度量提供了可以用于补偿主要和预驱动器开关噪声。

7. 发明申请

WO2014015071A3 REDUCING UNWANTED REFLECTIONS IN SOURCE-TERMINATED CHANNELS 审中-公开
公开(公告)号：WO2014015071A3
公开(公告)日：2014-01-23
申请号：PCT/US2013/050945
申请日：2013-07-17
申请人： RAMBUS INC.
发明人： OH, Kyung, Suk , VENKATESAN, Pravin, Kumar , FRANS, Yohan, Usthavia
IPC分类号： G11C7/00
摘要： A memory controller and/or memory device control termination of a communication link in order to achieve power savings while reducing or eliminating unwanted reflections in the channel. Following transmission of data over the communication channel, termination is left enabled for a programmable time period beginning immediately following completion of the transmission. The time period is sufficiently long to allow the unwanted reflections to be absorbed by the termination. Following the time period, the termination is disabled for power savings.

8. 发明授权

EP2115929B1 RECEIVER WITH CLOCK RECOVERY CIRCUIT AND ADAPTIVE SAMPLE AND EQUALIZER TIMING 有权转让
标题翻译： EMPFÄNGERMIT EINER TAKTWIEDERGEWINNUNGSSCHALTUNG UND ADAPTIVEM SAMPLE- UND ENTZERRERTIMING
公开(公告)号：EP2115929B1
公开(公告)日：2014-05-21
申请号：EP07853389.0
申请日：2007-12-13
申请人： Rambus Inc.
发明人： LIN, Qi , LEIBOWITZ, Brian , LEE, Hae-chang , REN, Jihong , OH, Kyung, Suk , ZERBE, Jared
IPC分类号： H04L7/02 , H04L7/00 , H04L25/03 , H04L7/033
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
摘要翻译：接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。样本和均衡器定时被转移到相对于当前符号具有较少的残余符号间干扰（ISI）能量的位置。可以使用信号质量的测量（诸如接收机误码率或滤波器抽头值的比较）来计算移位位置，以优化数据恢复的定时。

9. 发明公开

EP2583280A2 BALANCED ON-DIE TERMINATION 审中-公开
标题翻译：平衡式片上端接
公开(公告)号：EP2583280A2
公开(公告)日：2013-04-24
申请号：EP11796154.0
申请日：2011-06-01
申请人： Rambus Inc.
发明人： WILSON, John , KIM, Joong-Ho , KOLLIPARA, Ravindranath , SECKER, David , OH, Kyung, Suk
IPC分类号： G11C7/10
CPC分类号： G06F13/4086 , G06F13/4234
摘要： Termination of a high-speed signaling link is effected by simultaneously engaging on- die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link.

10. 发明公开

EP2115929A1 RECEIVER WITH CLOCK RECOVERY CIRCUIT AND ADAPTIVE SAMPLE AND EQUALIZER TIMING 有权转让
标题翻译：接收机时钟恢复电路和自适应采样和ENTZERRERTIMING
公开(公告)号：EP2115929A1
公开(公告)日：2009-11-11
申请号：EP07853389.0
申请日：2007-12-13
申请人： Rambus, Inc.
发明人： LIN, Qi , LEIBOWITZ, Brian , LEE, Hae-chang , REN, Jihong , OH, Kyung, Suk , ZERBE, Jared
IPC分类号： H04L7/02 , H04L7/00 , H04L25/03
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

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