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1. 发明申请

WO2012154507A1 SUPPORTING CALIBRATION FOR SUB-RATE OPERATION IN CLOCKED MEMORY SYSTEMS 审中-公开
标题翻译：支持在时钟记忆系统中进行子频率运算的校准
公开(公告)号：WO2012154507A1
公开(公告)日：2012-11-15
申请号：PCT/US2012/036370
申请日：2012-05-03
申请人： RAMBUS INC. , BANSAL, Akash , FRANS, Yohan U. , KASAMSETTY, Kishore V. , BYSTROM, Todd , LI, Simon , VAIDYANATH, Arun
发明人： BANSAL, Akash , FRANS, Yohan U. , KASAMSETTY, Kishore V. , BYSTROM, Todd , LI, Simon , VAIDYANATH, Arun
IPC分类号： G11C7/00 , G06F1/04
CPC分类号： G11C7/22 , G06F1/10 , G11C7/222 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., 1/2, 1/4 or 1/8 of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.
摘要翻译：公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中相应的数据信号之间的延迟的全速率校准状态。接下来，时钟存储器系统使用全速率校准状态来计算子速率校准状态，其与子速率频率（例如，全速率的1/2速率，1/4或1/8）相关联频率）。当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

2. 发明申请

WO2012082274A2 TIMING-DRIFT CALIBRATION 审中-公开
标题翻译：时序移位校准
公开(公告)号：WO2012082274A2
公开(公告)日：2012-06-21
申请号：PCT/US2011/060213
申请日：2011-11-10
申请人： RAMBUS INC. , FRANS, Yohan, U. , ELLIS, Wayne, F. , BANSAL, Akash
发明人： FRANS, Yohan, U. , ELLIS, Wayne, F. , BANSAL, Akash
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C29/50012 , G01R23/02 , G01R23/15 , G01R35/005 , G06F1/08 , G06F1/12 , G06F11/1604 , G06F13/1689 , G11C7/04 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/18 , G11C29/023 , G11C29/028 , G11C2207/2254 , H03L1/02
摘要： The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.
摘要翻译：所公开的实施例涉及支持定时漂移校准的存储器系统的组件。在具体实施例中，该存储器系统包含存储器件（或多个器件），其包括可产生频率的时钟分配电路和振荡器电路，其中频率变化表示时钟分配电路的定时漂移。存储装置还包括被配置为测量振荡器电路的频率的测量电路。此外，存储器系统包含存储器控制器，该存储器控制器可向存储器件发送请求以触发存储器件以测量振荡器电路的频率。存储器控制器还被配置为从存储器件接收测量的频率，并使用测量的频率来确定存储器件中的定时漂移。

3. 发明申请

WO2011156041A1 INTEGRATED CIRCUIT DEVICE TIMING CALIBRATION 审中-公开
标题翻译：集成电路设备时序校准
公开(公告)号：WO2011156041A1
公开(公告)日：2011-12-15
申请号：PCT/US2011/029144
申请日：2011-03-21
申请人： RAMBUS INC. , OH, Kyung Suk , FRANS, Yohan U. , BANSAL, Akash , LEIBOWITZ, Brian S.
发明人： OH, Kyung Suk , FRANS, Yohan U. , BANSAL, Akash , LEIBOWITZ, Brian S.
IPC分类号： G11C7/22 , H04L7/00
CPC分类号： H03K5/135 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , H04L7/0008 , H04L7/02 , H04L7/033 , H04L7/10
摘要： Techniques for performing timing calibration for an integrated circuit (IC) device are described. During operation, a first integrated circuit device transmits a first calibration pattern having differently delayed rising edge transitions with respect to a timing reference. The first integrated circuit device additionally transmits a second calibration pattern having differently delayed falling edge transitions with respect to the timing reference. Next, the first integrated circuit generates a timing offset for transmitting data from the first integrated circuit device. This timing offset is derived from information received from a second integrated circuit device sampling the first calibration pattern and the second calibration pattern.
摘要翻译：描述了用于执行集成电路（IC）装置的定时校准的技术。在操作期间，第一集成电路装置相对于定时参考发送具有不同延迟的上升沿转变的第一校准模式。第一集成电路装置另外发送相对于定时参考具有不同延迟的下降沿跃迁的第二校准模式。接下来，第一集成电路产生用于从第一集成电路器件发送数据的定时偏移。该定时偏移是从对第一校准图案和第二校准图案采样的第二集成电路装置接收的信息导出的。

4. 发明申请

WO2008085964A3 ADAPTIVE CONTINUOUS-TIME LINE EQUALIZER FOR CORRECTING THE FIRST POST-CURSOR ISI 审中-公开
公开(公告)号：WO2008085964A3
公开(公告)日：2008-07-17
申请号：PCT/US2008/000249
申请日：2008-01-07
申请人： RAMBUS INC. , LEE, Hae-Chang , LEIBOWITZ, Brian, S. , KIZER, Jade, M. , GREER III, Thomas, H. , BANSAL, Akash
发明人： LEE, Hae-Chang , LEIBOWITZ, Brian, S. , KIZER, Jade, M. , GREER III, Thomas, H. , BANSAL, Akash
IPC分类号： H04L25/03
摘要： A receiver includes a continuous-time equalizer (120), a decision-feedback equalizer (DFE) (125), data and error sampling logic (130), and an adaptation engine (135). The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

5. 发明申请

WO2012118714A3 TIMING CALIBRATION FOR MULTIMODE I/O SYSTEMS 审中-公开
公开(公告)号：WO2012118714A3
公开(公告)日：2012-09-07
申请号：PCT/US2012/026583
申请日：2012-02-24
申请人： RAMBUS INC. , OH, Kyung, Suk , BANSAL, Akash
发明人： OH, Kyung, Suk , BANSAL, Akash
IPC分类号： G06F13/38 , G06F13/14 , G11C7/10 , G11C7/22
摘要： Integrated circuit devices that operate in different modes. In a low data rate mode, data is transferred between the integrated circuit devices at a low data rate, or no data is transferred at all. In a high data rate mode, data is transferred between integrated circuit devices at a high data rate. A transition mode facilitates the transition from the low data rate mode to the high data rate mode. During the transition mode data is transferred between the integrated circuit devices at an intermediate data rate greater than the low data rate but lower than the high data rate. Also during the transition mode, parameters affecting the transmission of data between the integrated circuit devices are calibrated at the high data rate.

6. 发明申请

WO2012115839A1 PROTOCOL FOR MEMORY POWER-MODE CONTROL 审中-公开
标题翻译：用于存储器功率模式控制的协议
公开(公告)号：WO2012115839A1
公开(公告)日：2012-08-30
申请号：PCT/US2012/025310
申请日：2012-02-15
申请人： RAMBUS INC. , ELLIS, Wayne F. , RICHARDSON, Wayne S. , BANSAL, Akash , WARE, Frederick A. , LAI, Lawrence , KASAMSETTY, Kishore Ven
发明人： ELLIS, Wayne F. , RICHARDSON, Wayne S. , BANSAL, Akash , WARE, Frederick A. , LAI, Lawrence , KASAMSETTY, Kishore Ven
IPC分类号： G11C7/10 , G11C11/4096 , G11C11/402 , G06F13/14
CPC分类号： G11C11/40615 , G06F1/3234 , G11C7/02 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C29/022 , G11C29/028
摘要： In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.
摘要翻译：在一个实施例中，存储器设备包括存储器核心和用于接收命令和数据的输入接收器。存储器装置还包括寄存器，用于存储指示输入接收器的子集是否响应于控制信号掉电的值。存储器控制器将命令和数据发送到存储器件。存储器控制器还发送该值以指示存储器件的输入接收器的子集是否响应于控制信号掉电。此外，响应于自我新命令，存储装置延迟进入自刷新操作，直到接收到接收到自刷新命令之后接收到的控制信号。

7. 发明申请

WO2008085964B1 ADAPTIVE CONTINUOUS-TIME LINE EQUALIZER FOR CORRECTING THE FIRST POST-CURSOR ISI 审中-公开
标题翻译：用于校正第一后期游标ISI的自适应连续线均衡器
公开(公告)号：WO2008085964B1
公开(公告)日：2008-12-24
申请号：PCT/US2008000249
申请日：2008-01-07
申请人： RAMBUS INC , LEE HAE-CHANG , LEIBOWITZ BRIAN S , KIZER JADE M , GREER III THOMAS H , BANSAL AKASH
发明人： LEE HAE-CHANG , LEIBOWITZ BRIAN S , KIZER JADE M , GREER III THOMAS H , BANSAL AKASH
IPC分类号： H04L25/03
CPC分类号： H04L25/03159 , H04B1/123 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03636
摘要： A receiver includes a continuous-time equalizer (120), a decision-feedback equalizer (DFE) (125), data and error sampling logic (130), and an adaptation engine (135). The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
摘要翻译：接收机包括连续时间均衡器（120），判决反馈均衡器（DFE）（125），数据和错误采样逻辑（130）以及自适应引擎（135）。接收机通过基于第一后光标ISI的测量建立适用于连续时间均衡器的均衡设置来校正与最近的数据符号（第一后期光标ISI）相关联的符号间干扰（ISI）。

8. 发明申请

WO2008085964A2 HIGH-SPEED SIGNALING SYSTEMS AND METHODS WITH ADAPTABLE, CONTINUOUS-TIME EQUALIZATION 审中-公开
标题翻译：高速信号系统和方法具有适应性，连续时间均衡
公开(公告)号：WO2008085964A2
公开(公告)日：2008-07-17
申请号：PCT/US2008000249
申请日：2008-01-07
申请人： RAMBUS INC , LEE HAE-CHANG , LEIBOWITZ BRIAN S , KIZER JADE M , GREER III THOMAS H , BANSAL AKASH
发明人： LEE HAE-CHANG , LEIBOWITZ BRIAN S , KIZER JADE M , GREER III THOMAS H , BANSAL AKASH
IPC分类号： H04L25/03
CPC分类号： H04L25/03159 , H04B1/123 , H04L25/03057 , H04L25/0307 , H04L25/03885 , H04L2025/03356 , H04L2025/03636
摘要： A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter- symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.
摘要翻译：接收机包括连续时间均衡器，判决反馈均衡器（DFE），数据和误差采样逻辑以及自适应引擎。接收机通过基于第一后视标ISI的度量建立连续时间均衡器的适当均衡设置来校正与最新数据符号（第一后光标ISI）相关联的符号间干扰（ISI）。

9. 发明申请

WO2012118714A2 TIMING CALIBRATION FOR MULTIMODE I/O SYSTEMS 审中-公开
标题翻译：多模I / O系统的时序校准
公开(公告)号：WO2012118714A2
公开(公告)日：2012-09-07
申请号：PCT/US2012026583
申请日：2012-02-24
申请人： RAMBUS INC , OH KYUNG SUK , BANSAL AKASH
发明人： OH KYUNG SUK , BANSAL AKASH
CPC分类号： G06F1/08 , G06F13/1689 , G11C7/1066 , G11C7/1093 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Integrated circuit devices that operate in different modes. In a low data rate mode, data is transferred between the integrated circuit devices at a low data rate, or no data is transferred at all. In a high data rate mode, data is transferred between integrated circuit devices at a high data rate. A transition mode facilitates the transition from the low data rate mode to the high data rate mode. During the transition mode data is transferred between the integrated circuit devices at an intermediate data rate greater than the low data rate but lower than the high data rate. Also during the transition mode, parameters affecting the transmission of data between the integrated circuit devices are calibrated at the high data rate.
摘要翻译：在不同模式下工作的集成电路器件。在低数据速率模式下，以低数据速率在集成电路设备之间传输数据，或完全没有数据传输。在高数据速率模式下，以高数据速率在集成电路器件之间传输数据。转换模式有助于从低数据速率模式转换到高数据速率模式。在转换模式期间，以大于低数据速率但低于高数据速率的中间数据速率在集成电路器件之间传送数据。而且在转换模式期间，在高数据速率下校准影响集成电路器件之间的数据传输的参数。

10. 发明申请

WO2012082274A3 TIMING-DRIFT CALIBRATION 审中-公开
标题翻译：定时漂移校准
公开(公告)号：WO2012082274A3
公开(公告)日：2012-08-16
申请号：PCT/US2011060213
申请日：2011-11-10
申请人： RAMBUS INC , FRANS YOHAN U , ELLIS WAYNE F , BANSAL AKASH
发明人： FRANS YOHAN U , ELLIS WAYNE F , BANSAL AKASH
IPC分类号： G11C7/22 , G11C7/10
CPC分类号： G11C29/50012 , G01R23/02 , G01R23/15 , G01R35/005 , G06F1/08 , G06F1/12 , G06F11/1604 , G06F13/1689 , G11C7/04 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/18 , G11C29/023 , G11C29/028 , G11C2207/2254 , H03L1/02
摘要： The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device.
摘要翻译：所公开的实施例涉及支持定时漂移校准的存储器系统的组件。在具体实施例中，该存储器系统包含存储器设备（或多个设备），其包括时钟分配电路和可产生频率的振荡器电路，其中频率的改变指示时钟分配电路的时序漂移。存储器件还包括被配置为测量振荡器电路的频率的测量电路。另外，存储器系统包含存储器控制器，该存储器控制器可以向存储器装置发送请求以触发存储器装置测量振荡器电路的频率。存储器控制器还被配置为从存储器装置接收测量的频率并且使用测量的频率来确定存储器装置中的时序漂移。

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