专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2013085811A1 RECEIVER WITH ENHANCED ISI MITIGATION 审中-公开
标题翻译：接收器具有增强的ISI缓解
公开(公告)号：WO2013085811A1
公开(公告)日：2013-06-13
申请号：PCT/US2012/067277
申请日：2012-11-30
申请人： RAMBUS INC.
发明人： HOSSAIN, Masum , REN, Jihong , ZERBE, Jared , ARYANFAR, Farshid
IPC分类号： H04L25/03 , H03M1/00
CPC分类号： G06F1/3203 , H04B1/12 , H04L7/0054 , H04L7/033 , H04L25/03006 , H04L25/03012 , H04L25/03057 , H04L25/03127 , H04L25/03146 , H04L25/03853 , H04L2025/03433
摘要： A receiver integrated circuit is disclosed that includes a filter and a linear equalization circuit. The filter has an input to receive a signal symbols a main tap and a pre-cursor tap to reduces a pre-cursor ISI acting on the data symbols. The linear equalization circuit couples to the output and cooperates with the filter to further reduce ISI.
摘要翻译：公开了一种接收机集成电路，其包括滤波器和线性均衡电路。滤波器具有用于接收主要抽头和前置光标抽头的信号符号的输入，以减少作用在数据符号上的前标ISI。线性均衡电路耦合到输出并与滤波器配合以进一步减少ISI。

2. 发明申请

WO2011008356A2 TECHNIQUES FOR ADJUSTING CLOCK SIGNALS TO COMPENSATE FOR NOISE 审中-公开
标题翻译：调整时钟信号以补偿噪音的技术
公开(公告)号：WO2011008356A2
公开(公告)日：2011-01-20
申请号：PCT/US2010/036792
申请日：2010-05-31
申请人： RAMBUS INC. , ZERBE, Jared , BATRA, Pradeep , LEIBOWITZ, Brian
发明人： ZERBE, Jared , BATRA, Pradeep , LEIBOWITZ, Brian
IPC分类号： H03K19/0175 , H04L25/02 , H03K5/1252
CPC分类号： H04L25/0264 , G06F1/10 , H03K5/1252
摘要： A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs.
摘要翻译：第一集成电路（IC）具有可调延迟电路和第一接口电路。向可调延迟电路提供第一时钟信号以产生提供给第一接口电路的延迟的时钟信号。第二IC具有电源电压检测电路和与第一IC传输数据的第二接口电路。电源电压检测电路向第一IC提供指示第二IC的电源电压中的噪声的噪声信号。可调节延迟电路根据噪声信号调整延迟的时钟信号的延迟。在其他实施例中，边缘彩色时钟信号通过使IC间的共同的高频抖动来减少集成电路（IC）之间的数据传输中的高频抖动的影响。在其他实施例中，电源电压用于在多个IC上产生时钟信号。

3. 发明授权

EP2115929B1 RECEIVER WITH CLOCK RECOVERY CIRCUIT AND ADAPTIVE SAMPLE AND EQUALIZER TIMING 有权转让
标题翻译： EMPFÄNGERMIT EINER TAKTWIEDERGEWINNUNGSSCHALTUNG UND ADAPTIVEM SAMPLE- UND ENTZERRERTIMING
公开(公告)号：EP2115929B1
公开(公告)日：2014-05-21
申请号：EP07853389.0
申请日：2007-12-13
申请人： Rambus Inc.
发明人： LIN, Qi , LEIBOWITZ, Brian , LEE, Hae-chang , REN, Jihong , OH, Kyung, Suk , ZERBE, Jared
IPC分类号： H04L7/02 , H04L7/00 , H04L25/03 , H04L7/033
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
摘要翻译：接收器配备有自适应相位偏移控制器和相关联的定时校准电路，其一起移动数据采样器和数字均衡器的定时。样本和均衡器定时被转移到相对于当前符号具有较少的残余符号间干扰（ISI）能量的位置。可以使用信号质量的测量（诸如接收机误码率或滤波器抽头值的比较）来计算移位位置，以优化数据恢复的定时。

4. 发明申请

WO2011041060A2 METHODS AND SYSTEMS FOR REDUCING SUPPLY AND TERMINATION NOISE IN PROGRAMMABLE DELAY LINES 审中-公开
标题翻译：减少可编程延迟线中的供应和终止噪声的方法和系统
公开(公告)号：WO2011041060A2
公开(公告)日：2011-04-07
申请号：PCT/US2010/047282
申请日：2010-08-31
申请人： RAMBUS INC. , SATARZADEH, Patrick , ZERBE, Jared , DALY, Barry
发明人： SATARZADEH, Patrick , ZERBE, Jared , DALY, Barry
IPC分类号： H03K5/13 , H03H11/26
CPC分类号： H03H11/265 , H03K5/131
摘要： Described are integrated-circuit delay lines that include regulated and unregulated delay elements connected in series. The regulated delay elements exhibit relatively long delays that are stable over process, voltage, and temperature. The unregulated delay elements exhibit relatively short delays with fine adjustment granularity. A multiplexer selects various numbers of the delay elements to provide a range of delay settings. The multiplexer includes a number of smaller multiplexers cascaded to minimize the lead-in delay of the delay element. The delay elements and multiplexer can be single-ended or complementary.
摘要翻译：描述的是集成电路延迟线，其包括串联连接的调节和非调节延迟元件。稳定的延迟元件表现出相对较长的延迟，其在过程，电压和温度上是稳定的。未调节的延迟元件表现出相对短的延迟，具有精细的调整粒度。多路复用器选择各种数量的延迟元件以提供一定范围的延迟设置。多路复用器包括多个较小的多路复用器级联以最小化延迟元件的导入延迟。延迟元件和复用器可以是单端或互补的。

5. 发明申请

WO2008150321A1 METHODS AND SYSTEMS FOR TRANSMITTING AUXILIARY DATA BY MODULATING PRE-EMPHASIS FILTER COEFFICIENTS 审中-公开
标题翻译：通过调整前置滤波器系数来传输辅助数据的方法和系统
公开(公告)号：WO2008150321A1
公开(公告)日：2008-12-11
申请号：PCT/US2008/003961
申请日：2008-03-25
申请人： RAMBUS INC. , KIM, Jaeha , LEE, Haechang , CHUN, Jung-Hoon , ZERBE, Jared
发明人： KIM, Jaeha , LEE, Haechang , CHUN, Jung-Hoon , ZERBE, Jared
IPC分类号： H04L5/04 , H04L25/03
CPC分类号： H04L25/03343 , H04B1/126 , H04L5/04 , H04L2025/03356 , H04L2025/03477 , H04L2025/03802
摘要： A signaling system supports main and auxiliary communication channels between integrated circuits (105,110) in the same direction over a single link (115). An equalizing transmitter (117) applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel (115). The transmitter modulates (133) at least one of the filter coefficients (155) with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver (120) ignores the apparent ISI to recover the main data, while an auxiliary receiver (135) detects (170) and demodulates (172) the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread- spectrum techniques to reduce the impact of the auxiliary data on the main data.
摘要翻译：信号系统通过单个链路（115）在相同方向上支持集成电路（105,110）之间的主和辅助通信信道。当通过通信信道（115）发送主数据时，均衡发射机（117）应用适当的滤波器系数来最小化符号间干扰的影响。发射机利用辅助数据调制（133）至少一个滤波器系数（155）以在所发送的信号中引起明显的ISI。辅助接收机（135）检测（170）并解调（172）明显的ISI以恢复辅助数据，主接收机（120）忽略恢复主数据的明显ISI。可以使用扩频技术对辅助数据进行编码，以减少辅助数据对主数据的影响。

6. 发明公开

EP2774151A1 DATA TRANSMISSION USING DELAYED TIMING SIGNALS 有权转让
标题翻译：与延迟时钟信号的通信
公开(公告)号：EP2774151A1
公开(公告)日：2014-09-10
申请号：EP12845819.7
申请日：2012-10-26
申请人： Rambus Inc.
发明人： WARE, Frederick A. , TSERN, Ely , LEIBOWITZ, Brian , ZERBE, Jared
IPC分类号： G11C7/00
CPC分类号： H03K5/13 , G06F13/00 , G06F13/1689 , G06F13/4243 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/22 , G11C29/022 , G11C29/023 , G11C29/028
摘要： An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

7. 发明公开

EP1588571A2 METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM 有权
标题翻译：方法和设备进行评价和信号系统优化
公开(公告)号：EP1588571A2
公开(公告)日：2005-10-26
申请号：EP02801043.7
申请日：2002-10-11
申请人： RAMBUS INC.
发明人： ZERBE, Jared , CHAU, Pak, Shing , STONECYPHER, William, Franklin
IPC分类号： H04Q1/00
CPC分类号： G01R31/31717 , G01R31/31703 , G01R31/3183 , G06F11/221 , H04B3/32
摘要： A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit (101) circuit of the system and is transmitted to a receive (103) circuit. A similar pattern of information is generated in the receive (103) circuit and used as a reference. The receive (103) circuit compares the patterns. Any differences (114) between the patterns are observable. In one embodiment, a linear feedback shift (105, 108) register (LFSR) implemented to produce patterns. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

8. 发明授权

EP1588571B1 METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM 有权
标题翻译：方法和设备进行评价和信号系统优化
公开(公告)号：EP1588571B1
公开(公告)日：2010-12-15
申请号：EP02801043.7
申请日：2002-10-11
申请人： Rambus Inc.
发明人： ZERBE, Jared , CHAU, Pak, Shing , STONECYPHER, William, Franklin
IPC分类号： G01R31/28
CPC分类号： G01R31/31717 , G01R31/31703 , G01R31/3183 , G06F11/221 , H04B3/32
摘要： A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit (101) circuit of the system and is transmitted to a receive (103) circuit. A similar pattern of information is generated in the receive (103) circuit and used as a reference. The receive (103) circuit compares the patterns. Any differences (114) between the patterns are observable. In one embodiment, a linear feedback shift (105, 108) register (LFSR) implemented to produce patterns. An embodiment of the invention may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the invention may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

9. 发明公开

EP2115929A1 RECEIVER WITH CLOCK RECOVERY CIRCUIT AND ADAPTIVE SAMPLE AND EQUALIZER TIMING 有权转让
标题翻译：接收机时钟恢复电路和自适应采样和ENTZERRERTIMING
公开(公告)号：EP2115929A1
公开(公告)日：2009-11-11
申请号：EP07853389.0
申请日：2007-12-13
申请人： Rambus, Inc.
发明人： LIN, Qi , LEIBOWITZ, Brian , LEE, Hae-chang , REN, Jihong , OH, Kyung, Suk , ZERBE, Jared
IPC分类号： H04L7/02 , H04L7/00 , H04L25/03
CPC分类号： H04L25/03254 , H04L7/0025 , H04L7/0054 , H04L7/0058 , H04L7/0087 , H04L7/033 , H04L7/0331 , H04L25/03057 , H04L25/03885 , H04L43/028 , H04L2025/03617
摘要： A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.

10. 发明授权

EP2774151B1 DATA TRANSMISSION USING DELAYED TIMING SIGNALS 有权转让
公开(公告)号：EP2774151B1
公开(公告)日：2019-08-14
申请号：EP12845819.7
申请日：2012-10-26
申请人： Rambus Inc.
发明人： WARE, Frederick A. , TSERN, Ely , LEIBOWITZ, Brian , ZERBE, Jared
IPC分类号： G11C7/00 , G11C7/10 , G11C29/02 , G06F13/16 , G11C7/04 , G11C7/22 , H03K5/13

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式