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1. 发明申请

WO2013081572A3 METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER 审中-公开
标题翻译：减少时钟抖动的方法和电路
公开(公告)号：WO2013081572A3
公开(公告)日：2013-08-08
申请号：PCT/US2011054615
申请日：2011-10-03
申请人： RAMBUS INC , ZERBE JARED , STONE TEVA , REN JIHONG
发明人： ZERBE JARED , STONE TEVA , REN JIHONG
IPC分类号： H03K5/1252
CPC分类号： H04L7/02 , H03K5/1252 , H03L7/00
摘要： A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.
摘要翻译：通信系统包括时钟转发路径中的连续时间线性均衡器。可以调整均衡器以使时钟抖动最小化，包括在使能时钟信号之后与前几个时钟沿相关联的抖动。降低早期的抖动可以降低功耗和电路复杂度，否则需要快速打开系统。

2. 发明申请

WO2013006231A3 LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER 审中-公开
标题翻译：低延迟，频率敏捷的时钟倍频器
公开(公告)号：WO2013006231A3
公开(公告)日：2013-04-04
申请号：PCT/US2012039268
申请日：2012-05-24
申请人： RAMBUS INC , ZERBE JARED L , LEIBOWITZ BRIAN S , HOSSAIN MASUM
发明人： ZERBE JARED L , LEIBOWITZ BRIAN S , HOSSAIN MASUM
IPC分类号： H03K5/00 , H03B19/00
CPC分类号： H03L7/16 , H03J2200/10 , H03K3/0315 , H03K5/00006 , H03K5/13 , H03K5/14 , H03L7/06 , H03L7/0995 , H03L7/24
摘要： In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally- staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.
摘要翻译：在第一时钟倍频器中，并行操作具有光谱交错锁定范围的多个注入锁定振荡器（ILO），以实现比单独ILO的集中输入频率范围宽得多的集中输入频率范围。在每个输入频率改变之后，可以根据一个或多个合格标准评估ILO输出时钟，以选择ILO中的一个作为最终时钟源。在第二个时钟倍频器中，柔性注入速率注入锁定振荡器锁定超级谐波，次谐波或频率注入脉冲，在不同的注入脉冲速率之间无缝切换，以实现宽泛的输入频率范围。由第一和/或第二时钟倍频器响应于输入时钟而实现的倍频因子被实时确定，然后与编程的（期望的）倍增因子进行比较以在倍频的不同分频实例之间进行选择时钟。

3. 发明申请

WO2012151050A2 INTEGRATED CIRCUIT HAVING A MULTIPLYING INJECTION-LOCKED OSCILLATOR 审中-公开
标题翻译：具有多针注射锁止振荡器的集成电路
公开(公告)号：WO2012151050A2
公开(公告)日：2012-11-08
申请号：PCT/US2012034074
申请日：2012-04-18
申请人： RAMBUS INC , ZERBE JARED L , DALY BARRY W , DUNWELL DUSTIN T , CARUSONE ANTHONY C , EBLE III JOHN C
发明人： ZERBE JARED L , DALY BARRY W , DUNWELL DUSTIN T , CARUSONE ANTHONY C , EBLE III JOHN C
IPC分类号： H03B27/00 , H03L7/24
CPC分类号： H03L7/24 , H03B27/00 , H03K3/0315 , H03K3/0322 , H03K5/133 , H03K5/1565
摘要： Methods and apparatuses featuring a multiplying injection- locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection- locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection- locked oscillator. In embodiments that include multiple injection- locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection- locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection- locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.
摘要翻译：描述了具有乘法注入锁定振荡器的方法和装置。一些实施例包括脉冲发生器和注射器以及一个或多个注射锁定振荡器。脉冲发生器和注射器的输出可以注入注射锁定振荡器的相应注入点。在包括多个注入锁定振荡器的实施例中，每个注入锁定振荡器的输出可以被注入下一个注入锁定振荡器的相应注入点。一些实施例通过动态修改注入锁定振荡器的环路长度和/或通过使用占空比校正器和/或通过复用/混合来自注入锁定振荡器的多个延迟元件的输出来减少确定性抖动。

4. 发明申请

WO2012021380A2 FAST-WAKE MEMORY 审中-公开
标题翻译：快速存储器
公开(公告)号：WO2012021380A2
公开(公告)日：2012-02-16
申请号：PCT/US2011046669
申请日：2011-08-04
申请人： RAMBUS INC , WARE FREDERICK A , ZERBE JARED L , LEIBOWITZ BRIAN S
发明人： WARE FREDERICK A , ZERBE JARED L , LEIBOWITZ BRIAN S
IPC分类号： G11C7/22 , G06F12/00 , G06F13/16 , G11C7/10
CPC分类号： G06F1/3275 , G06F1/324 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G06F2213/0038 , G11C5/14 , G11C5/148 , G11C7/04 , G11C7/22 , G11C7/222 , G11C11/4072 , G11C11/4076 , G11C2207/2227 , G11C2207/2254
摘要： One or more timing signals used to time data and command transmission over highspeed data and command signaling links are paused or otherwise disabled when a memory system enters a low-power state, and require substantial time to be re-established at appropriate frequency and/or phase as the system returns to an active operating state. Instead of waiting for the high-speed timing signals to be re-established before beginning memory access operations, an alternative, lower-frequency timing source is used to time transfer of one or more memory-access commands over a combination of data and command signaling links while the high-speed timing signals are being restored, thereby hastening transmission of memory-access commands to memory devices and reducing the incremental latency required to exit the low-power state. A timing signal generators capable of glitchlessly shifting a timing signal between two or more oscillation frequencies may also (or alternatively) be provided, thus enabling different- frequency timing signals to be delivered to system components via the same timing signal paths in either operating state. When the timing signal is used to time data (or command) transfer over information-bearing signaling links, the ability to glitchlessly shift the timing signal frequency enables a corresponding glitchless shift between lower and higher data rates on the information-bearing signaling links.
摘要翻译：当存储器系统进入低功率状态并且需要大量时间以适当的频率重新建立时，用于对高速数据和命令信令链路上的数据和命令传输进行计时的一个或多个定时信号被暂停或以其他方式禁用和/或阶段，因为系统返回到活动的操作状态。代替在开始存储器访问操作之前等待高速定时信号被重新建立，替代的较低频率的定时源被用于通过数据和命令信令的组合来定时传送一个或多个存储器访问命令而高速定时信号正在恢复，从而加快了对存储器设备的存储器访问命令的传输，并减少了退出低功耗状态所需的增量等待时间。也可以（或者替代地）提供能够在两个或更多个振荡频率之间无故障地移位定时信号的定时信号发生器，从而使得不同频率定时信号能够在任一操作状态下经由相同定时信号路径被传送到系统组件。当使用定时信号来对通过信息承载的信令链路进行数据（或命令）传输时，无信号地改变定时信号频率的能力使信息承载信令链路上的较低和较高数据速率之间的相应无毛刺移位成为可能。

5. 发明申请

WO2011062823A3 RECEIVER WITH TIME-VARYING THRESHOLD VOLTAGE 审中-公开
标题翻译：具有时变门限电压的接收器
公开(公告)号：WO2011062823A3
公开(公告)日：2011-08-18
申请号：PCT/US2010056213
申请日：2010-11-10
申请人： RAMBUS INC , ZERBE JARED L , LEIBOWITZ BRIAN S , LIN QI
发明人： ZERBE JARED L , LEIBOWITZ BRIAN S , LIN QI
IPC分类号： G11C5/14 , G11C7/10 , G11C7/22
CPC分类号： H03K3/013 , G11C7/02 , H03K5/153 , H04L25/03057 , H04L25/066 , H04L25/4902 , H04L25/4917
摘要： A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.
摘要翻译：描述了用于在电路之间传送信息的系统。发射电路通过通信信道向接收器提供脉冲幅度调制（PAM）信号。接收机中的电路使用时变阈值电压从接收信号中确定数字值，该阈值电压在比特时间内变化。这种方法可以补偿符号间干扰（ISI）以增加系统的电压和时间裕度。

6. 发明申请

WO2010078384A4 METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMS 审中-公开
标题翻译：在高速信号系统中瞬时事件中校正相位误差的方法和装置
公开(公告)号：WO2010078384A4
公开(公告)日：2010-11-04
申请号：PCT/US2009069760
申请日：2009-12-29
申请人： RAMBUS INC , ZERBE JARED L
发明人： ZERBE JARED L
IPC分类号： H04L7/033 , H04L27/18
CPC分类号： H04L7/0083 , H03L7/07 , H03L7/0807 , H03L7/0814 , H04L7/0008
摘要： A system for dynamically correcting phase errors between data and a timing reference signal caused by a transient event during data communication between a transmitter and a receiver is described. During operation, the system stores one or more phase-offset values for the event in an offset table, wherein the constituent phase-offset values are associated with phase error caused by the event. Upon detecting a subsequent occurrence of the event, the system adjusts a phase relationship between the data and the timing reference signal based on the one or more phase-offset values.
摘要翻译：描述了一种用于动态校正在发射机和接收机之间的数据通信期间由瞬态事件引起的数据与定时参考信号之间的相位误差的系统。在操作期间，系统将一个或多个事件的相位偏移值存储在偏移表中，其中相位偏移值与由事件引起的相位错误相关联。在检测到事件的随后发生时，系统基于一个或多个相位偏移值来调整数据与定时参考信号之间的相位关系。

7. 发明申请

WO2009111175A1 ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION 审中-公开
标题翻译：多线通信期间的错误检测和偏移消除
公开(公告)号：WO2009111175A1
公开(公告)日：2009-09-11
申请号：PCT/US2009/034494
申请日：2009-02-19
申请人： RAMBUS INC. , KIZER, Jade, M. , WILSON, John , LUO, Lei , WARE, Frederick , ZERBE, Jared, L.
发明人： KIZER, Jade, M. , WILSON, John , LUO, Lei , WARE, Frederick , ZERBE, Jared, L.
IPC分类号： H04L25/49
CPC分类号： H03M13/47 , H04L25/4919
摘要： Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.
摘要翻译：描述电路的实施例。在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。另外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡，以及M个符号集合中的第二值的多个实例，并且如果不平衡是检测到，这会导致错误条件。

8. 发明申请

WO2009058790A1 SIGNALING WITH SUPERIMPOSED DIFFERENTIAL-MODE AND COMMON-MODE SIGNALS 审中-公开
标题翻译：信号与超级差分模式和共模信号
公开(公告)号：WO2009058790A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/081478
申请日：2008-10-28
申请人： RAMBUS INC. , LIN, Qi , LEE, Hae-Chang , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
发明人： LIN, Qi , LEE, Hae-Chang , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
IPC分类号： H04L5/20
CPC分类号： H04L25/0272 , H04L5/20 , H04L25/0262
摘要： A data receiver circuit (206) includes first and second interfaces (221) coupled to first and second respective transmission lines (204). The first and second respective transmission lines comprise a pair of transmission lines external to the data receiver circuit. The first and second interfaces receive a transmission signal from the pair of transmission lines. A common mode extraction circuit (228) is coupled to the first and second interfaces to extract a common-mode clock signal from the received transmission signal. A differential mode circuit (238) is coupled to the first and second interfaces to extract a differential-mode data signal from the received transmission signal. The extracted data signal has a symbol rate corresponding to a frequency of the extracted clock signal (e.g.,- the symbol rate may be twice the frequency of the extracted clock signal). The differential mode circuit is synchronized to the extracted clock signal.
摘要翻译：数据接收器电路（206）包括耦合到第一和第二相应传输线（204）的第一和第二接口（221）。第一和第二相应的传输线包括数据接收器电路外部的一对传输线。第一和第二接口从一对传输线接收传输信号。共模提取电路（228）耦合到第一和第二接口以从接收到的传输信号中提取共模时钟信号。差分模式电路（238）耦合到第一和第二接口以从接收到的传输信号中提取差分模式数据信号。所提取的数据信号具有对应于所提取的时钟信号的频率的符号率（例如，符号率可以是提取的时钟信号的频率的两倍）。差分模式电路与提取的时钟信号同步。

9. 发明申请

WO2009058789A1 SIGNALING WITH SUPERIMPOSED CLOCK AND DATA SIGNALS 审中-公开
标题翻译：用超级时钟和数据信号进行信号
公开(公告)号：WO2009058789A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/081477
申请日：2008-10-28
申请人： RAMBUS INC. , LIN, Qi , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
发明人： LIN, Qi , KIM, Jaeha , LEIBOWITZ, Brian, S. , ZERBE, Jared, L. , REN, Jihong
IPC分类号： H04L7/027 , H04L7/00
CPC分类号： H04L7/0008 , H04L7/065 , H04L25/0276 , H04L25/14
摘要： A data transmission circuit includes a clock driver to obtain a clock signal having a first rate and to drive the clock signal onto one or more transmission lines. The data transmission circuit also includes a timing circuit to obtain the clock signal and to generate a symbol clock having a second rate. The first rate is a multiple of the second rate, wherein the multiple is greater than one. The data transmission circuit further includes a data driver synchronized to the symbol clock. The data driver obtains a data signal and drives the data signal onto the one or more transmission lines at the second rate. The data signal and the clock signal are driven onto the one or more transmission lines simultaneously.
摘要翻译：数据传输电路包括时钟驱动器，以获得具有第一速率的时钟信号并将时钟信号驱动到一条或多条传输线上。数据传输电路还包括一个定时电路以获得时钟信号并产生具有第二速率的符号时钟。第一速率是第二速率的倍数，其中倍数大于1。数据传输电路还包括与符号时钟同步的数据驱动器。数据驱动器获得数据信号，并以第二速率将数据信号驱动到一条或多条传输线上。数据信号和时钟信号同时被驱动到一个或多个传输线上。

10. 发明申请

WO2009003129A3 METHODS AND CIRCUITS FOR ADAPTIVE EQUALIZATION AND CHANNEL CHARACTERIZATION USING LIVE DATA 审中-公开
标题翻译：使用实时数据的自适应均衡和通道特征的方法和电路
公开(公告)号：WO2009003129A3
公开(公告)日：2009-04-16
申请号：PCT/US2008068409
申请日：2008-06-26
申请人： RAMBUS INC , LEE HAE-CHANG , REN JIHONG , LEIBOWITZ BRIAN S , MADDEN CHRISTOPHER J , LIN QI , ZERBE JARED L
发明人： LEE HAE-CHANG , REN JIHONG , LEIBOWITZ BRIAN S , MADDEN CHRISTOPHER J , LIN QI , ZERBE JARED L
IPC分类号： H04L25/02 , H04L1/20 , H04L25/03
CPC分类号： H04L25/03878 , H04L1/203 , H04L1/205 , H04L25/0224 , H04L25/0242 , H04L25/0264 , H04L25/0272 , H04L25/03012 , H04L25/03343
摘要： A communication system supports high-speed communication over a signal lane that extends between respective transmitting and receiving integrated circuit (IC) devices. One or both of the IC devices includes an equalizer to offset channel characteristics that otherwise impair speed performance. A margining circuit on the receiving IC measures a timing margin of the received signal and adjusts the equalization settings for one or both transmitters to maximize the timing margin. Another embodiment compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex error analysis and adaptation circuitry on the higher-performance side of the lane. The error analysis and adaptation circuitry reduces the error margin of the transmitted signal to introduce bit errors at the receiver, analyzes the bit errors to measure ISI imposed by the channel, and adjusts voltage offsets of the continuous-time signal to compensate for the ISI. In some embodiments the receiver calculates the system response for diagnostics and for computing equalization settings.
摘要翻译：通信系统支持在相应的发送和接收集成电路（IC）设备之间延伸的信号通道上的高速通信。一个或两个IC器件包括均衡器以抵消否则会影响速度性能的通道特性。接收IC上的边缘电路测量接收信号的定时裕度，并调整一个或两个发射机的均衡设置以使定时裕度最大化。另一实施例通过在车道的较高性能侧实例化相对复杂的误差分析和适配电路来补偿通过双向通道通信的IC之间的性能不对称性。误差分析和自适应电路减少发射信号的误差容限，在接收机引入位错误，分析位误差以测量通道施加的ISI，并调整连续时间信号的电压补偿以补偿ISI。在一些实施例中，接收机计算用于诊断和计算均衡设置的系统响应。

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