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1. 发明申请

US20050059216A1 METHOD OF MAKING DIRECT CONTACT ON GATE BY USING DIELECTRIC STOP LAYER 失效
标题翻译：通过使用介质停止层在门上制造直接接触的方法
公开(公告)号：US20050059216A1
公开(公告)日：2005-03-17
申请号：US10664211
申请日：2003-09-17
申请人： Purakh Verma , Sanford Chu , Lap Chan , Yelehanka Ramachandramurthy Pradeep , Kai Shao , Jia Zheng
发明人： Purakh Verma , Sanford Chu , Lap Chan , Yelehanka Ramachandramurthy Pradeep , Kai Shao , Jia Zheng
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (f.,), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作时的噪声性能，增加的单位功率增益频率（f。）和减小的栅极延迟。

2. 发明申请

US20050136573A1 Method of making direct contact on gate by using dielectric stop layer 有权
标题翻译：通过使用介电阻挡层在栅极上直接接触的方法
公开(公告)号：US20050136573A1
公开(公告)日：2005-06-23
申请号：US11045958
申请日：2005-01-28
申请人： Purakh Rajverma , Sanford Chu , Lap Chan , Yelehanka Ramachandramurthy Pradeep , Kai Shao , Jia Zheng
发明人： Purakh Rajverma , Sanford Chu , Lap Chan , Yelehanka Ramachandramurthy Pradeep , Kai Shao , Jia Zheng
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/4763 , H01L21/768 , H01L21/84 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76802 , H01L21/76829
摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (fmax), and reduced gate delay.
摘要翻译：描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作下的噪声性能，增加的单位功率增益频率（f max）和减小的栅极延迟。

3. 发明授权

US06852605B2 Method of forming an inductor with continuous metal deposition 有权
公开(公告)号：US06852605B2
公开(公告)日：2005-02-08
申请号：US10427287
申请日：2003-05-01
申请人： Chit Hwei Ng , Lap Chan , Purakh Verma , Yelehanka Ramachandramurthy Pradeep , Sanford Chu
发明人： Chit Hwei Ng , Lap Chan , Purakh Verma , Yelehanka Ramachandramurthy Pradeep , Sanford Chu
IPC分类号： H01F17/00 , H01L21/02 , H01L23/522 , H01L21/20
CPC分类号： H01L28/10 , H01F17/0006 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.

4. 发明申请

US20050124131A1 Method of forming an inductor with continuous metal deposition 审中-公开
标题翻译：形成具有连续金属沉积的电感器的方法
公开(公告)号：US20050124131A1
公开(公告)日：2005-06-09
申请号：US11034932
申请日：2005-01-13
申请人： Chit Hweing , Lap Chan , Purakh Verma , Yelehanka Ramachandramurthy Pradeep , Sanford Chu
发明人： Chit Hweing , Lap Chan , Purakh Verma , Yelehanka Ramachandramurthy Pradeep , Sanford Chu
IPC分类号： H01F17/00 , H01L21/02 , H01L23/522 , H01L21/20 , H01L29/00
CPC分类号： H01L28/10 , H01F17/0006 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.
摘要翻译：描述了在硅衬底上制造RF电感器件的方法。沉积低k或其他电介质材料并图案化以形成电感器下板沟槽。沟槽衬有阻挡膜，如填充有铜的TaN和使用化学机械抛光（CMP）平坦化的多余金属。介电材料的第二层被沉积并图案化以形成通孔/沟槽。通孔/沟槽图案填充有阻挡材料，蚀刻通孔/沟槽之间的电介质膜以形成第二组沟槽。这些沟槽用铜填充并平坦化。电介质膜的第三层被沉积并图案化以形成通孔/沟槽。然后用阻挡材料填充通孔/沟槽，蚀刻通孔/沟槽图案之间的电介质膜以形成第三组沟槽。这些沟槽填充有铜金属，并通过CMP去除多余的金属以形成所述RF电感器。

5. 发明授权

US06821904B2 Method of blocking nitrogen from thick gate oxide during dual gate CMP 失效
公开(公告)号：US06821904B2
公开(公告)日：2004-11-23
申请号：US10209151
申请日：2002-07-30
申请人： Yelehanka Ramachandramurthy Pradeep , Sanford Chu , Chit Hwei Ng , Jia Zhen Zheng , Purakh Verma
发明人： Yelehanka Ramachandramurthy Pradeep , Sanford Chu , Chit Hwei Ng , Jia Zhen Zheng , Purakh Verma
IPC分类号： H01L21302
CPC分类号： H01L21/823857 , H01L21/3144
摘要： In accordance with the objectives of the invention a new method is provided for the creation of layers of gate oxide having an unequal thickness. Active surface regions are defined over the surface of a substrate, a thick layer of gate oxide is grown over the active surface. A selective etch is applied to the thick layer of gate oxide, selectively reducing the thickness of the thick layer of gate oxide to the required thickness of a thin layer of gate oxide. The layer of thick gate oxide is blocked from exposure. N2 atoms are implanted into the exposed surface of the thin layer of oxide, rapid thermal processing is performed and the blocking mask is removed from the surface of the thick layer of gate oxide. A high concentration of nitride has now been provided in the thin layer of gate oxide.

6. 发明授权

US06716693B1 Method of forming a surface coating layer within an opening within a body by atomic layer deposition 有权
标题翻译：通过原子层沉积在体内的开口内形成表面涂层的方法
公开(公告)号：US06716693B1
公开(公告)日：2004-04-06
申请号：US10400511
申请日：2003-03-27
申请人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
发明人： Lap Chan , Sanford Chu , Chit Hwei Ng , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
IPC分类号： H01L218234
CPC分类号： H01L28/10 , H01F17/0033 , H01F41/042 , H01L21/76838 , H01L23/522 , H01L23/5227 , H01L23/53238 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： An improved new process for fabricating multilevel interconnected vertical channels and horizontal channels or tunnels. The method has broad applications in semiconductors, for copper interconnects and inductors, as well as, in the field of bio-sensors for mini- or micro-columns in gas or liquid separation, gas/liquid chromatography, and in capillary separation techniques. In addition, special techniques are described to deposit by atomic layer deposition, ALD, a copper barrier layer and seed layer for electroless copper plating, filling trench and channel or tunnel openings in a type of damascene process, to form copper interconnects and inductors.
摘要翻译：一种用于制造多层互连垂直通道和水平通道或隧道的改进的新工艺。该方法在半导体，铜互连和电感器以及在气体或液体分离中的微型或微型柱的生物传感器领域，气/液相色谱和毛细管分离技术领域具有广泛的应用。此外，描述了通过原子层沉积，ALD，铜阻挡层和用于化学镀铜的种子层，一种镶嵌工艺中的填充沟槽和沟道或隧道开口来沉积特殊技术以形成铜互连和电感器。

7. 发明授权

US06468877B1 Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner 有权
标题翻译：通过使用一次性间隔件/衬垫在栅电极的边缘下形成气隙的方法
公开(公告)号：US06468877B1
公开(公告)日：2002-10-22
申请号：US09907651
申请日：2001-07-19
申请人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
发明人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
IPC分类号： H01L2176
CPC分类号： H01L21/7682 , H01L21/764 , H01L21/823468 , H01L29/4983
摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.
摘要翻译：一种制造半导体器件的气隙间隔物的方法，包括以下步骤。提供具有至少一对限定有源区域的STI的半导体衬底。在有源区内的基板上形成栅电极。栅电极具有底层栅介电层。在该结构上形成衬里氧化物层，覆盖栅极电介质层的侧壁，栅电极以及栅电极的顶表面。在衬垫氧化物层上形成衬里氮化物层。在结构上形成厚的氧化物层。厚氧化物，衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化，并且在栅电极的任一侧暴露衬里氧化物层。用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层，以在栅电极的任一侧上形成横截面倒置的T形开口。在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层，其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口，并且其中气隙间隔物邻近倒置的底部形成 T形开口。蚀刻栅间隔氧化物，衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。

8. 发明授权

US06455377B1 Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) 失效
标题翻译：通过SiGe或多量子阱（MQW）的选择性沉积形成非常高迁移率的垂直沟道晶体管的方法
公开(公告)号：US06455377B1
公开(公告)日：2002-09-24
申请号：US09765040
申请日：2001-01-19
申请人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
发明人： Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/1054 , H01L29/66916 , H01L29/7827 , H01L29/802
摘要： A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench. A gate conductor layer is formed on the gate dielectric layer, filling the gate trench.
摘要翻译：一种制造垂直沟道晶体管的方法，包括以下步骤。提供具有上表面的半导体衬底。在半导体衬底上形成高掺杂N型下部外延硅层。在下部外延硅层上形成低掺杂P型中间外延硅层。在中间外延硅层上形成高掺杂N型上部外延硅层。蚀刻下部，中间和上部外延硅层以形成由隔离沟槽限定的外延层堆叠。在隔离槽内形成氧化物。氧化物被蚀刻以在一个隔离沟槽内形成栅极沟槽，暴露外延层堆叠面向栅极沟槽的侧壁。在暴露的外延层堆叠侧壁上形成多量子阱或染色层超晶格。在多量子阱或染色层超晶格上并在栅极沟槽内形成栅介质层。栅极导体层形成在栅极电介质层上，填充栅极沟槽。

9. 发明授权

US06440800B1 Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers 失效
公开(公告)号：US06440800B1
公开(公告)日：2002-08-27
申请号：US09769814
申请日：2001-01-26
申请人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
发明人： James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/365 , H01L29/7827
摘要： A method for a vertical transistor by selective epi deposition to form the conductive source, drain, and channel layers. The conductive source, drain, and channel layers are preferably formed by a selective epi process. Dielectric masks define the conductive layers and make areas to form vertical contacts to the conductive S/D and channel layers.

10. 发明授权

US06541327B1 Method to form self-aligned source/drain CMOS device on insulated staircase oxide 失效
标题翻译：在绝缘阶梯氧化物上形成自对准源极/漏极CMOS器件的方法
公开(公告)号：US06541327B1
公开(公告)日：2003-04-01
申请号：US09760123
申请日：2001-01-16
申请人： Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
发明人： Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung , Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng
IPC分类号： H01L218238
CPC分类号： H01L29/66492 , H01L21/823814 , H01L29/41783 , H01L29/665 , H01L29/66575
摘要： A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.
摘要翻译：一种在绝缘层中的阶梯形开口形成升高的源极/漏极（S / D）的方法。栅极结构形成在衬底上。栅极结构优选由栅极电介质层，栅电极，第一间隔物和硬掩模组成。在衬底和栅极结构之上形成第一绝缘层。形成抗蚀剂层，其具有在栅极结构上方的开口以及与栅极结构相邻的横向区域。我们通过抗蚀剂层中的开口蚀刻绝缘层。蚀刻去除绝缘层的第一厚度以形成源极/漏极（S / D）开口。我们移除第一个垫片和硬掩模以形成一个源极/漏极（S / D）接触开口。我们通过源极/漏极（S / D）接触开口将离子注入到衬底中，以形成轻掺杂的漏极区。我们在源极/漏极（S / D）接触开口和源极/漏极（S / D）开口中的栅电极和栅极电介质的侧壁和绝缘层的侧壁上形成第二间隔物。在栅电极，绝缘层上沉积导电层。导电层被平坦化以暴露绝缘层，以在阶梯形绝缘层上形成升高的源极/漏极（S / D）块。

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