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1. 发明授权

US6134516A Simulation server system and method 失效
标题翻译：仿真服务器系统及方法
公开(公告)号：US6134516A
公开(公告)日：2000-10-17
申请号：US19384
申请日：1998-02-05
申请人： Steven Wang , Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Ren-Song Tsay , Richard Yachyang Sun , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai
发明人： Steven Wang , Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Ren-Song Tsay , Richard Yachyang Sun , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022 , G06F17/5027
摘要： The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. A Simulation server in accordance with an embodiment of the present invention allows multiple users to access the same reconfigurable hardware unit to effectively simulate and accelerate the same or different user designs in a time-shared manner in both a network and a non-network environment. The server provides the multiple users or processes to access the reconfigurable hardware unit for acceleration and hardware state swapping purposes. The Simulation server includes the scheduler, one or more device drivers, and the reconfigurable hardware unit. The scheduler in the Simulation server is based on a preemptive round robin algorithm. The server scheduler includes a simulation job queue table, a priority sorter, and a job swapper.
摘要翻译： SEMulation系统提供四种操作模式：（1）软件仿真，（2）通过硬件加速模拟，（3）在线仿真（ICE）和（4）后仿真分析。在高水平上，本发明可以以上述四种模式或这些模式的各种组合来体现。这些模式的核心是控制该系统整体运行的软件内核。内核的主控制循环执行以下步骤：初始化系统，评估主动测试台过程/组件，评估时钟组件，检测时钟边沿，更新寄存器和存储器，传播组合组件，提前模拟时间，并继续循环只要存在有效的测试台过程。根据本发明的实施例的仿真服务器允许多个用户访问相同的可重配置硬件单元，以在网络和非网络环境中以时间共享的方式有效地模拟和加速相同或不同的用户设计。服务器提供多个用户或进程来访问可重新配置的硬件单元，以实现加速和硬件状态交换的目的。模拟服务器包括调度程序，一个或多个设备驱动程序和可重新配置的硬件单元。模拟服务器中的调度器基于抢占式循环算法。服务器调度程序包括模拟作业队列表，优先级排序器和作业交换器。

2. 发明授权

US6009256A Simulation/emulation system and method 失效
公开(公告)号：US6009256A
公开(公告)日：1999-12-28
申请号：US850136
申请日：1997-05-02
申请人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Richard Yachyang Sun , Mike Mon Yen Tsai , Ren-Song Tsay , Steven Wang
发明人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Richard Yachyang Sun , Mike Mon Yen Tsai , Ren-Song Tsay , Steven Wang
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5027 , G06F17/5022
摘要： The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. Each mode or combination of modes provides the following main features or combinations of main features: (1) switching among modes, manually or automatically; (2) compilation process to generate software models and hardware models; (3) component type analysis for generating hardware models; (4) software clock set-up to avoid race conditions through, in one embodiment, gated clock logic analysis and gated data logic analysis; (5) software clock implementation through, in one embodiment, clock edge detection in the software model to trigger an enable signal in the hardware model, send signal from the primary clock to the clock input of the clock edge register in the hardware model via the gated clock logic, send a clock enable signal to the enable input of the hardware model's register, send data from the primary clock register to the hardware model's register via the gated data logic, and reset the clock edge register disabling the clock enable signal to the enable input of the hardware model's registers; (6) log selective data for debug sessions and post-simulation analysis; and (7) combinational logic regeneration.

3. 发明授权

US08352924B2 Method and device for multi-core instruction-set simulation 有权
标题翻译：多核指令集仿真的方法和装置
公开(公告)号：US08352924B2
公开(公告)日：2013-01-08
申请号：US12588324
申请日：2009-10-13
申请人： Meng-Huan Wu , Cheng-Yang Fu , Peng-Chih Wang , Ren-Song Tsay
发明人： Meng-Huan Wu , Cheng-Yang Fu , Peng-Chih Wang , Ren-Song Tsay
IPC分类号： G06F9/45
CPC分类号： G06F17/5022 , G06F8/53 , G06F9/4552 , G06F2217/68
摘要： The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.
摘要翻译：本发明公开了一种多核指令集仿真方法。所提出的方法识别共享数据段和不同核心之间的依赖关系，从而有效减少同步点数量，降低同步开销，从而允许更多地执行多核指令集仿真，同时确保仿真结果是准确的此外，本发明还公开了一种用于多核指令集仿真的装置。

4. 发明申请

US20110197174A1 Method, System and Computer Readable Medium for Generating Software Transaction-Level Modeling (TLM) Model 有权
标题翻译：用于生成软件事务级建模（TLM）模型的方法，系统和计算机可读介质
公开(公告)号：US20110197174A1
公开(公告)日：2011-08-11
申请号：US12701810
申请日：2010-02-08
申请人： Meng-Huan WU , Ren-Song Tsay
发明人： Meng-Huan WU , Ren-Song Tsay
IPC分类号： G06F9/45
CPC分类号： G06F8/53
摘要： The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model.
摘要翻译：本发明公开了一种生成软件TLM模型的系统，包括处理单元; 耦合到所述处理单元以生成目标软件的目标二进制代码的编译器; 反编译器，其耦合到所述处理单元以将所述目标二进制代码反编译为高级代码，例如C或C ++代码，以生成所述目标软件的功能模型，其中所述功能模型包括多个基本块; 执行时间计算模块，耦合到所述处理单元，以计算所述功能模型的所述多个基本块的总执行时间; 耦合到所述处理单元的同步点识别模块，以识别所述软件交易级建模模型的同步点; 以及耦合到处理单元的时间注释模块，以将基本块和同步点的总体执行时间注释到功能模型中以获得软件事务级建模模型。

5. 发明申请

US20120191441A1 High-Parallelism Synchronization Approach for Multi-Core Instruction-Set Simulation 有权
标题翻译：用于多核指令集仿真的高并行同步方法
公开(公告)号：US20120191441A1
公开(公告)日：2012-07-26
申请号：US13011942
申请日：2011-01-24
申请人： Meng-Huan Wu , Ren-Song Tsay
发明人： Meng-Huan Wu , Ren-Song Tsay
IPC分类号： G06F9/455
CPC分类号： G06F17/5022 , G06F9/52 , G06F2217/68
摘要： The present invention discloses a high-parallelism synchronization method for multi-core instruction-set simulation. The proposed method utilizes a new distributed scheduling mechanism for a parallel compiled MCISS. The proposed method can enhance the parallelism of the MCISS so that the computing power of a multi-core host machine can be effectively utilized. The distributed scheduling with the present invention's prediction method significantly shortens the waiting time which an ISS spends on synchronization
摘要翻译：本发明公开了一种用于多核指令集仿真的高并行同步方法。所提出的方法利用并行编译的MCISS的新的分布式调度机制。所提出的方法可以增强MCISS的并行性，从而可以有效利用多核主机的计算能力。利用本发明的预测方法的分布式调度大大缩短了ISS花费在同步上的等待时间

6. 发明申请

US20120185231A1 Cycle-Count-Accurate (CCA) Processor Modeling for System-Level Simulation 审中-公开
标题翻译：用于系统级仿真的循环计数精确（CCA）处理器建模
公开(公告)号：US20120185231A1
公开(公告)日：2012-07-19
申请号：US13008921
申请日：2011-01-19
申请人： Chen-Kang LO , Li-Chun Chen , Meng-Huan Wu , Ren-Song Tsay
发明人： Chen-Kang LO , Li-Chun Chen , Meng-Huan Wu , Ren-Song Tsay
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/68
摘要： The present invention discloses a cycle-count-accurate (CCA) processor modeling, which can achieve high simulation speeds while maintaining timing accuracy of the system simulation. The CCA processor modeling includes a pipeline subsystem model and a cache subsystem model with accurate cycle with accurate cycle count information and guarantees accurate timing and functional behaviors on processor interface. The CCA processor modeling further includes a branch predictor and a bus interface (BIF) to predict the branch of pipeline execution behavior (PEB) and to simulate the data accesses between the processor and the external components via an external bus, respectively. The experimental results show that the CCA processor modeling performs 50 times faster than the corresponding Cycle-accurate (CA) model while providing the same cycle count information as the target RTL model.
摘要翻译：本发明公开了一种循环计数精确（CCA）处理器建模，可以实现高仿真速度，同时保持系统仿真的定时精度。 CCA处理器建模包括管道子系统模型和具有精确周期的缓存子系统模型，具有精确的周期计数信息，并保证处理器接口上的精确时序和功能行为。 CCA处理器建模还包括分支预测器和总线接口（BIF），以预测流水线执行行为（PEB）的分支，并分别通过外部总线模拟处理器与外部组件之间的数据访问。实验结果表明，CCA处理器建模比相应的周期精确（CA）模型快50倍，同时提供与目标RTL模型相同的周期计数信息。

7. 发明授权

US08549468B2 Method, system and computer readable storage device for generating software transaction-level modeling (TLM) model 有权
标题翻译：用于生成软件事务级建模（TLM）模型的方法，系统和计算机可读存储设备
公开(公告)号：US08549468B2
公开(公告)日：2013-10-01
申请号：US12701810
申请日：2010-02-08
申请人： Meng-Huan Wu , Ren-Song Tsay
发明人： Meng-Huan Wu , Ren-Song Tsay
IPC分类号： G06F9/44
CPC分类号： G06F8/53
摘要： The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model.
摘要翻译：本发明公开了一种生成软件TLM模型的系统，包括处理单元; 耦合到所述处理单元以生成目标软件的目标二进制代码的编译器; 反编译器，其耦合到所述处理单元以将所述目标二进制代码反编译为高级代码，例如C或C ++代码，以生成所述目标软件的功能模型，其中所述功能模型包括多个基本块; 执行时间计算模块，耦合到所述处理单元，以计算所述功能模型的所述多个基本块的总执行时间; 耦合到所述处理单元的同步点识别模块，以识别所述软件交易级建模模型的同步点; 以及耦合到处理单元的时间注释模块，以将基本块和同步点的总体执行时间注释到功能模型中以获得软件事务级建模模型。

8. 发明申请

US20120233410A1 Shared-Variable-Based (SVB) Synchronization Approach for Multi-Core Simulation 审中-公开
标题翻译：基于共享变量（SVB）的多核仿真同步方法
公开(公告)号：US20120233410A1
公开(公告)日：2012-09-13
申请号：US13046743
申请日：2011-03-13
申请人： Cheng-Yang FU , Meng-Huan Wu , Ren-Song Tsay
发明人： Cheng-Yang FU , Meng-Huan Wu , Ren-Song Tsay
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0837
摘要： The present invention discloses a shared-variable-based (SVB) approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach, synchronizing at either every cycle or memory access, gives accurate simulation results, it has poor performance due to huge simulation overloads. In the present invention, timing synchronization is only needed before shared variable accesses in order to maintain accuracy while improving the efficiency in the proposed shared-variable-based approach.
摘要翻译：本发明公开了一种用于快速准确的多核高速缓存一致性模拟的共享变量（SVB）方法。虽然直观的常规方法，在每个周期或存储器访问同步，给出精确的模拟结果，由于巨大的模拟过载，它的性能不佳。在本发明中，仅在共享变量访问之前需要定时同步，以便在提出基于共享变量的方法中提高效率的同时保持准确性。

9. 发明申请

US20120197625A1 Data-dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling 审中-公开
标题翻译：基于数据依赖性的建模方法，用于高效地模拟OS抢占式调度
公开(公告)号：US20120197625A1
公开(公告)日：2012-08-02
申请号：US13016933
申请日：2011-01-28
申请人： Peng-Chih WANG , Meng-Huan Wu , Ren-Song Tsay
发明人： Peng-Chih WANG , Meng-Huan Wu , Ren-Song Tsay
IPC分类号： G06F9/45
CPC分类号： G06F9/485 , G06F17/5022
摘要： In the present disclosure, the DOM approach for the simulation of OS preemptive scheduling has presented and demonstrated. By maintaining the data-dependency between the software tasks, and guaranteeing the order of shared variable accesses, it can accurately simulate the preemption effect. Moreover, the proposed DOM OS model is implemented to enable preemptive scheduling in SystemC.
摘要翻译：在本公开中，用于模拟OS抢占式调度的DOM方法已经呈现并展示出来。通过维护软件任务之间的数据依赖关系，保证共享变量访问的顺序，可以准确模拟抢占效果。此外，提出的DOM OS模型被实现为在SystemC中启用抢占式调度。

10. 发明申请

US20130054854A1 Full Bus Transaction Level Modeling Approach for Fast and Accurate Contention Analysis 审中-公开
标题翻译：完整的总线交易级建模方法，用于快速准确的竞争分析
公开(公告)号：US20130054854A1
公开(公告)日：2013-02-28
申请号：US13398083
申请日：2012-02-16
申请人： Mao-Lin Li , Chen-Kang Lo , Li-Chun Chen , Hong-Jie Huang , Jen-Chieh Yeh , Ren-Song Tsay
发明人： Mao-Lin Li , Chen-Kang Lo , Li-Chun Chen , Hong-Jie Huang , Jen-Chieh Yeh , Ren-Song Tsay
IPC分类号： G06F13/362
CPC分类号： G06F13/362 , G06F13/1642
摘要： The present invention presents an effective Cycle-count Accurate Transaction level (CCA-TLM) full bus modeling and simulation technique. Using the two-phase arbiter and master-slave models, an FSM-based Composite Master-Slave-pair and Arbiter Transaction (CMSAT) model is proposed for efficient and accurate dynamic simulations. This approach is particularly effective for bus architecture exploration and contention analysis of complex Multi-Processor System-on-Chip (MPSoC) designs.
摘要翻译：本发明提出了一种有效的循环计数精确交易级别（CCA-TLM）全总线建模和仿真技术。使用两相仲裁器和主从模型，提出了基于FSM的复合主从从对和仲裁器事务（CMSAT）模型，用于高效和准确的动态模拟。这种方法对于复杂的多处理器片上系统（MPSoC）设计的总线架构探索和竞争分析特别有效。

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