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1. 发明授权

US6134516A Simulation server system and method 失效
标题翻译：仿真服务器系统及方法
公开(公告)号：US6134516A
公开(公告)日：2000-10-17
申请号：US19384
申请日：1998-02-05
申请人： Steven Wang , Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Ren-Song Tsay , Richard Yachyang Sun , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai
发明人： Steven Wang , Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Ren-Song Tsay , Richard Yachyang Sun , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022 , G06F17/5027
摘要： The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. A Simulation server in accordance with an embodiment of the present invention allows multiple users to access the same reconfigurable hardware unit to effectively simulate and accelerate the same or different user designs in a time-shared manner in both a network and a non-network environment. The server provides the multiple users or processes to access the reconfigurable hardware unit for acceleration and hardware state swapping purposes. The Simulation server includes the scheduler, one or more device drivers, and the reconfigurable hardware unit. The scheduler in the Simulation server is based on a preemptive round robin algorithm. The server scheduler includes a simulation job queue table, a priority sorter, and a job swapper.
摘要翻译： SEMulation系统提供四种操作模式：（1）软件仿真，（2）通过硬件加速模拟，（3）在线仿真（ICE）和（4）后仿真分析。在高水平上，本发明可以以上述四种模式或这些模式的各种组合来体现。这些模式的核心是控制该系统整体运行的软件内核。内核的主控制循环执行以下步骤：初始化系统，评估主动测试台过程/组件，评估时钟组件，检测时钟边沿，更新寄存器和存储器，传播组合组件，提前模拟时间，并继续循环只要存在有效的测试台过程。根据本发明的实施例的仿真服务器允许多个用户访问相同的可重配置硬件单元，以在网络和非网络环境中以时间共享的方式有效地模拟和加速相同或不同的用户设计。服务器提供多个用户或进程来访问可重新配置的硬件单元，以实现加速和硬件状态交换的目的。模拟服务器包括调度程序，一个或多个设备驱动程序和可重新配置的硬件单元。模拟服务器中的调度器基于抢占式循环算法。服务器调度程序包括模拟作业队列表，优先级排序器和作业交换器。

2. 发明授权

US6009256A Simulation/emulation system and method 失效
公开(公告)号：US6009256A
公开(公告)日：1999-12-28
申请号：US850136
申请日：1997-05-02
申请人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Richard Yachyang Sun , Mike Mon Yen Tsai , Ren-Song Tsay , Steven Wang
发明人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Richard Yachyang Sun , Mike Mon Yen Tsai , Ren-Song Tsay , Steven Wang
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5027 , G06F17/5022
摘要： The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. Each mode or combination of modes provides the following main features or combinations of main features: (1) switching among modes, manually or automatically; (2) compilation process to generate software models and hardware models; (3) component type analysis for generating hardware models; (4) software clock set-up to avoid race conditions through, in one embodiment, gated clock logic analysis and gated data logic analysis; (5) software clock implementation through, in one embodiment, clock edge detection in the software model to trigger an enable signal in the hardware model, send signal from the primary clock to the clock input of the clock edge register in the hardware model via the gated clock logic, send a clock enable signal to the enable input of the hardware model's register, send data from the primary clock register to the hardware model's register via the gated data logic, and reset the clock edge register disabling the clock enable signal to the enable input of the hardware model's registers; (6) log selective data for debug sessions and post-simulation analysis; and (7) combinational logic regeneration.

3. 发明授权

US09195784B2 Common shared memory in a verification system 有权
标题翻译：验证系统中的共享共享内存
公开(公告)号：US09195784B2
公开(公告)日：2015-11-24
申请号：US13078786
申请日：2011-04-01
申请人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai , Steven Wang
发明人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai , Steven Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5027 , G06F17/5031 , G06F2217/68 , G06F2217/84 , G06F2217/86
摘要： The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.
摘要翻译：本专利说明书中描述的调试系统提供了一种从通常不可合成的代码元件产生硬件元件的系统，用于放置在FPGA器件上。这个特定的FPGA器件被称为行为处理器。该行为处理器以硬件方式执行先前在软件中执行的代码结构。当需要工作站或软件模型进行干预的某些条件（例如，如果...然后... else循环）时，行为处理器与Xtrigger设备一起发送回呼信号到工作站以立即响应。

4. 发明授权

US08244512B1 Method and apparatus for simulating a circuit using timing insensitive glitch-free (TIGF) logic 有权
标题翻译：用于使用时序不敏感无毛刺（TIGF）逻辑模拟电路的方法和装置
公开(公告)号：US08244512B1
公开(公告)日：2012-08-14
申请号：US09954989
申请日：2001-09-12
申请人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai , Steven Wang
发明人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai , Steven Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5027 , G06F2217/86
摘要： The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.
摘要翻译：本专利说明书中描述的调试系统提供了一种从通常不可合成的代码元件产生硬件元件的系统，用于放置在FPGA器件上。这个特定的FPGA器件被称为行为处理器。该行为处理器以硬件方式执行先前在软件中执行的代码结构。当需要工作站或软件模型进行干预的某些条件（例如，如果...然后... else循环）时，行为处理器与Xtrigger设备一起发送回呼信号到工作站以立即响应。

5. 发明申请

US20110307233A1 COMMON SHARED MEMORY IN A VERIFICATION SYSTEM 有权
标题翻译：通用系统中的共享共享内存
公开(公告)号：US20110307233A1
公开(公告)日：2011-12-15
申请号：US13078786
申请日：2011-04-01
申请人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai , Steven Wang
发明人： Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai , Steven Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5027 , G06F17/5031 , G06F2217/68 , G06F2217/84 , G06F2217/86
摘要： The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.
摘要翻译：本专利说明书中描述的调试系统提供了一种从通常不可合成的代码元件产生硬件元件的系统，用于放置在FPGA器件上。这个特定的FPGA器件被称为行为处理器。该行为处理器以硬件方式执行先前在软件中执行的代码结构。当需要工作站或软件模型进行干预的某些条件（例如，如果...然后... else循环）时，行为处理器与Xtrigger设备一起发送回呼信号到工作站以立即响应。

6. 发明授权

US06810442B1 Memory mapping system and method 有权
标题翻译：内存映射系统和方法
公开(公告)号：US06810442B1
公开(公告)日：2004-10-26
申请号：US09954275
申请日：2001-09-12
申请人： Sharon Sheau-Pyng Lin , Ping-Sheng Tseng
发明人： Sharon Sheau-Pyng Lin , Ping-Sheng Tseng
IPC分类号： G06F1328
CPC分类号： G06F17/5022 , G06F17/5027 , G06F2217/86
摘要： A debug system generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device for used in electronic design automation (EDA). The FPGA device (Behavior Processor) operates to execute in hardware code constructs previously executed in software. When some condition is satisfied (e.g. If . . . then . . . else loop) requiring intervention, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response. A memory block from a logic device is mapped to a memory device in a re-configurable hardware unit using a memory mapping system including a conductive connector driver, a memory block interface, and evaluation logic in each logic device, the connector driver, the interface, and the connector controller, the evaluation logic providing control signals used to evaluate data in the hardware model and to control write/read memory access between the logic device and the memory device via the driver and interface.
摘要翻译：调试系统从通常不可合成的代码元素生成用于放置在用于电子设计自动化（EDA）的FPGA设备上的硬件元件。 FPGA器件（行为处理器）操作以先前在软件中执行的硬件代码结构执行。当需要干预的某些条件（例如If ...然后... else循环）时，行为处理器使用Xtrigger设备向工作站发送回呼信号以立即响应。使用存储器映射系统将来自逻辑设备的存储器块映射到可重新配置的硬件单元中的存储器件，该存储器映射系统包括每个逻辑器件中的导电连接器驱动器，存储器块接口和评估逻辑，连接器驱动器，接口以及所述连接器控制器，所述评估逻辑提供用于评估所述硬件模型中的数据的控制信号，以及经由所述驱动器和接口来控制所述逻辑设备和所述存储器设备之间的写入/读取存储器访问。

7. 发明授权

US6026230A Memory simulation system and method 失效
标题翻译：内存模拟系统和方法
公开(公告)号：US6026230A
公开(公告)日：2000-02-15
申请号：US19328
申请日：1998-02-05
申请人： Sharon Sheau-Pyng Lin , Ping-Sheng Tseng
发明人： Sharon Sheau-Pyng Lin , Ping-Sheng Tseng
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022 , G06F17/5027
摘要： The SEmulation system provides four modes of operation: (1) Software Simulation, (2) Simulation via Hardware Acceleration, (3) In-Circuit Emulation (ICE), and (4) Post-Simulation Analysis. At a high level, the present invention may be embodied in each of the above four modes or various combinations of these modes. At the core of these modes is a software kernel which controls the overall operation of this system. The main control loop of the kernel executes the following steps: initialize system, evaluate active test-bench processes/components, evaluate clock components, detect clock edge, update registers and memories, propagate combinational components, advance simulation time, and continue the loop as long as active test-bench processes are present. The Memory Mapping aspect of the invention provides a structure and scheme where the numerous memory blocks associated with the user's design is mapped into the SRAM memory devices in the Simulation system instead of inside the logic devices, which are used to configure and model the user's design. The Memory Mapping or Memory Simulation system includes a memory state machine, an evaluation state machine, and their associated logic to control and interface with: (1) the main computing system and its associated memory system, (2) the SRAM memory devices coupled to the FPGA buses in the Simulation system, and (3) the FPGA logic devices which contain the configured and programmed user design that is being debugged.
摘要翻译： SEMulation系统提供四种操作模式：（1）软件仿真，（2）通过硬件加速模拟，（3）在线仿真（ICE）和（4）后仿真分析。在高水平上，本发明可以以上述四种模式或这些模式的各种组合来体现。这些模式的核心是控制该系统整体运行的软件内核。内核的主控制循环执行以下步骤：初始化系统，评估主动测试台过程/组件，评估时钟组件，检测时钟边沿，更新寄存器和存储器，传播组合组件，提前模拟时间，并继续循环只要存在有效的测试台过程。本发明的存储器映射方面提供了一种结构和方案，其中与用户设计相关联的多个存储块被映射到仿真系统中的SRAM存储器件中，而不是用于配置和建模用户设计的逻辑器件内部。存储器映射或存储器模拟系统包括存储器状态机，评估状态机及其相关逻辑以控制和接口：（1）主计算系统及其相关的存储器系统，（2）SRAM存储器件耦合到仿真系统中的FPGA总线，以及（3）包含已调试的配置和编程用户设计的FPGA逻辑器件。

8. 发明授权

US06651225B1 Dynamic evaluation logic system and method 失效
标题翻译：动态评估逻辑系统及方法
公开(公告)号：US06651225B1
公开(公告)日：2003-11-18
申请号：US09546554
申请日：2000-04-10
申请人： Sharon Sheau-Pyng Lin , Ping-Sheng Tseng , Chwen-Cher Chang , Su-Jen Hwang
发明人： Sharon Sheau-Pyng Lin , Ping-Sheng Tseng , Chwen-Cher Chang , Su-Jen Hwang
IPC分类号： G06F1750
CPC分类号： G06F17/5027 , G06F17/5022
摘要： In a verification system, a dynamic logic evaluation system and method dynamically calculates the minimum evaluation time for each input. Thus, this system and method will remove the performance burden that a fixed and statically calculated evaluation time would introduce. By dynamically calculating different evaluation times based on the input, 99% of the inputs will not be delayed for the sake of 1% of the inputs that actually need the worst possible evaluation time. The dynamic logic evaluation system and method comprises a global control unit coupled to a propagation detector, where the propagation detector is placed in each FPGA chip. The propagation detector in the FPGA chip alerts the global control unit of any input data that is currently propagating within the FPGA chips. A master clock controls the operation of this dynamic evaluation system and method. As long as any input data is propagating, the global control unit will prevent the next input from being provided to the FPGA chips for evaluation. Once the output has stabilized, the global control unit will then instruct the system to accept and process the next set of input data. Thus, the global control unit in conjunction with the propagation detectors can dynamically provide varying evaluation time periods based on the needs of the input data. Whether the system needs longer or shorter evaluation times, the system will dynamically adjust the amount of time necessary to properly process that input and then move on to the next evaluation time for the next set of inputs.
摘要翻译：在验证系统中，动态逻辑评估系统和方法动态地计算每个输入的最小评估时间。因此，该系统和方法将消除固定和静态计算的评估时间将引入的性能负担。通过根据输入动态计算不同的评估时间，为了实际需要最差可能的评估时间的1％的输入，99％的输入将不会被延迟。动态逻辑评估系统和方法包括耦合到传播检测器的全局控制单元，其中传播检测器被放置在每个FPGA芯片中。 FPGA芯片中的传播检测器向全局控制单元报告当前在FPGA芯片内传播的任何输入数据。主时钟控制这种动态评估系统和方法的运行。只要任何输入数据正在传播，全局控制单元将阻止将下一个输入提供给FPGA芯片进行评估。一旦输出稳定，全局控制单元将指示系统接受并处理下一组输入数据。因此，全局控制单元结合传播检测器可以基于输入数据的需要动态地提供变化的评估时间段。无论系统是否需要更长或更短的评估时间，系统将动态调整正确处理该输入所需的时间量，然后进入下一组输入的下一个评估时间。

9. 发明授权

US06389379B1 Converification system and method 失效
公开(公告)号：US06389379B1
公开(公告)日：2002-05-14
申请号：US09096865
申请日：1998-06-12
申请人： Sharon Sheau-Pyng Lin , Ping-Sheng Tseng
发明人： Sharon Sheau-Pyng Lin , Ping-Sheng Tseng
IPC分类号： G06F9455
CPC分类号： G06F17/5022 , G06F17/5027
摘要： The coverification system includes a reconfigurable computing system (hereinafter “RCC computing system”) and a reconfigurable computing hardware array (hereinafter “RCC hardware array”). In some embodiments, the target system and the external I/O devices are not necessary since they can be modeled in software. In other embodiments, the target system and the external I/O devices are actually coupled to the coverification system to obtain speed and use actual data, rather than simulated test bench data. The RCC computing system contains a CPU and memory for processing data for modeling the entire user design in software. The RCC computing system also contains clock logic (for clock edge detection and software clock generation), test bench processes for testing the user design, and device models for any I/O device that the user decides to model in software instead of using an actual physical I/O device. The user may decide to use actual I/O devices as well as modeled I/O devices in one debug session. The software clock is used as the external clock source for the target system and the external I/O devices to synchronize all data that is delivered between the coverification system and the external interface. The coverification system contains a control logic that provides traffic control between: (1) the RCC computing system and the RCC hardware array, and (2) the external interface (which are coupled to the target system and the external I/O devices) and the RCC hardware array. Because the RCC computing system has the model of the entire design in software, including that portion of the user design modeled in the RCC hardware array, the RCC computing system must also have access to all data that passes between the external interface and the RCC hardware array. The control logic ensures that the RCC computing system has access to these data. Pointers are used to latch data from the RCC computing system and the external interface to the internal nodes of the hardware model in the RCC hardware array. Pointers are also used to deliver data from the internal nodes of the hardware model to the RCC computing system and the external interface. Even if the data from the internal nodes of the hardware model is intended for the external interface, the RCC computing system must also be able to access this data as well.

10. 发明授权

US06421251B1 Array board interconnect system and method 失效
公开(公告)号：US06421251B1
公开(公告)日：2002-07-16
申请号：US09019383
申请日：1998-02-05
申请人： Sharon Sheau-Pyng Lin
发明人： Sharon Sheau-Pyng Lin
IPC分类号： H05K710
CPC分类号： G06F17/5022 , G06F17/5027
摘要： The FPGA array in the Simulation system is provided on the motherboard through a particular board interconnect structure to provide easy expandability and maximize packaging density with a single PCB design. Each chip may have up to eight sets of interconnections, where the interconnections are arranged according to adjacent direct-neighbor interconnects (i.e., N[73:0], S[73:0], W[73:0], E[73:0]), and one-hope neighbor interconnects (i.e., NH[27:0], SH[27:0], XH[36:0], XH[72:37]), excluding the local bus connections, within a single board and across different boards. Each chip is capable of being interconnected directly to adjacent neighbor chips, or in one hop to a non-adjacent chip located above, below, left, and right. In the X direction (east-west), the array is connected in a torus. In the Y direction (north-south), the array is connected in a column. The interconnects alone can couple logic devices and other components within a single board. However, the inter-board connectors are provided to couple these boards and interconnects together across different boards to carry signals between (1) the PCI bus via the motherboard and the array boards, and (2) any two array boards, all without passing through a backplane or motherboard to achieve the highest packaging density. A motherboard connector connects the board to the motherboard, and hence, to the PCI bus, power, and ground. For some boards, the motherboard connector is not used for direct connection to the motherboard. In a six-board configuration, only boards 1, 3 and 5 are directly connected to the motherboard while the remaining boards 2, 4, and 6 rely on their neighbor boards for motherboard connectivity. Thus, every other board is directly connected to the motherboard, and interconnects and local buses of these boards are coupled together via inter-board connectors arranged solder-side to component-side. PCI signals are routed through one of the boards (typically the first board) only. Power and ground are applied to the other motherboard connectors for those boards. Placed solder-side to component-side, the various inter-board connectors allow communication among the PCI bus components, the FPGA logic devices, memory devices, and various Simulation system control circuits.

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