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1. 发明申请

US20110218791A1 System for Simulating Processor Power Consumption and Method of the Same 审中-公开
标题翻译：用于模拟处理器功耗的系统及其方法
公开(公告)号：US20110218791A1
公开(公告)日：2011-09-08
申请号：US12716446
申请日：2010-03-03
申请人： Chien-Min LEE , Chen-Kang Lo , Meng-Huan Wu , Ren-Song Tsay
发明人： Chien-Min LEE , Chen-Kang Lo , Meng-Huan Wu , Ren-Song Tsay
IPC分类号： G06G7/62
CPC分类号： G06G7/62
摘要： The present invention provides a method for simulating processor power consumption, the method comprises: simulating a simulated processor; utilizing a power analysis model to analyze the simulated processor's execution of at least one fragment of a program, for generating power analysis of a plurality of basic blocks of the at least one fragment; computing at least one power correction factor between the plurality of basic block; utilizing a processing apparatus to generate a simulation model with power annotation based on the power analysis and the at least one power correction factor; and predicting power consumption of the simulated processor based on the simulation model with power annotation.
摘要翻译：本发明提供了一种用于模拟处理器功耗的方法，所述方法包括：模拟模拟处理器; 利用功率分析模型来分析所述模拟处理器对程序的至少一个片段的执行，以产生所述至少一个片段的多个基本块的功率分析; 计算所述多个基本块之间的至少一个功率校正因子; 利用处理装置基于功率分析和至少一个功率校正因子来生成具有功率注释的仿真模型; 并基于具有功率注释的仿真模型预测模拟处理器的功耗。

2. 发明申请

US20100269103A1 Method and device for multi-core instruction-set simulation 有权
标题翻译：多核指令集仿真的方法和装置
公开(公告)号：US20100269103A1
公开(公告)日：2010-10-21
申请号：US12588324
申请日：2009-10-13
申请人： Meng-Huan Wu , Cheng-Yang Fu , Peng-Chih Wang , Ren-Song Tsay
发明人： Meng-Huan Wu , Cheng-Yang Fu , Peng-Chih Wang , Ren-Song Tsay
IPC分类号： G06F9/45
CPC分类号： G06F17/5022 , G06F8/53 , G06F9/4552 , G06F2217/68
摘要： The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.
摘要翻译：本发明公开了一种多核指令集仿真方法。所提出的方法识别共享数据段和不同核心之间的依赖关系，从而有效减少同步点数量，降低同步开销，从而允许更多地执行多核指令集仿真，同时确保仿真结果是准确的此外，本发明还公开了一种用于多核指令集仿真的装置。

3. 发明授权

US08549468B2 Method, system and computer readable storage device for generating software transaction-level modeling (TLM) model 有权
标题翻译：用于生成软件事务级建模（TLM）模型的方法，系统和计算机可读存储设备
公开(公告)号：US08549468B2
公开(公告)日：2013-10-01
申请号：US12701810
申请日：2010-02-08
申请人： Meng-Huan Wu , Ren-Song Tsay
发明人： Meng-Huan Wu , Ren-Song Tsay
IPC分类号： G06F9/44
CPC分类号： G06F8/53
摘要： The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model.
摘要翻译：本发明公开了一种生成软件TLM模型的系统，包括处理单元; 耦合到所述处理单元以生成目标软件的目标二进制代码的编译器; 反编译器，其耦合到所述处理单元以将所述目标二进制代码反编译为高级代码，例如C或C ++代码，以生成所述目标软件的功能模型，其中所述功能模型包括多个基本块; 执行时间计算模块，耦合到所述处理单元，以计算所述功能模型的所述多个基本块的总执行时间; 耦合到所述处理单元的同步点识别模块，以识别所述软件交易级建模模型的同步点; 以及耦合到处理单元的时间注释模块，以将基本块和同步点的总体执行时间注释到功能模型中以获得软件事务级建模模型。

4. 发明申请

US20130234998A1 STYLUS 有权
公开(公告)号：US20130234998A1
公开(公告)日：2013-09-12
申请号：US13775262
申请日：2013-02-25
申请人： Jen-Yu Wang , Wei-Cheng Lo , Yu-Chia Chang , Meng-Huan Wu , Chia-Hao Chang
发明人： Jen-Yu Wang , Wei-Cheng Lo , Yu-Chia Chang , Meng-Huan Wu , Chia-Hao Chang
IPC分类号： H01Q1/52 , G06F3/0354
CPC分类号： H01Q1/52 , G06F3/03545 , H01Q1/44 , H01Q9/0421
摘要： A stylus includes a conductive rod, a circuit board, and an antenna. The conductive rod has a first opening. The circuit board is disposed in the conductive rod and includes a ground portion, wherein the conductive rod is electrically connected to the ground portion. The antenna includes a radiating portion and a feeding portion. The feeding portion is electrically connected to the circuit board and extends to the outside of the conductive rod via the first opening. The radiating portion is disposed at the outside of the conductive rod and is electrically connected to the feeding portion.
摘要翻译：触针包括导电棒，电路板和天线。导电棒具有第一开口。电路板设置在导电棒中并且包括接地部分，其中导电棒电连接到接地部分。天线包括辐射部分和馈送部分。馈电部分电连接到电路板，并经由第一开口延伸到导电棒的外部。辐射部分设置在导电棒的外侧并与馈电部分电连接。

5. 发明申请

US20120233410A1 Shared-Variable-Based (SVB) Synchronization Approach for Multi-Core Simulation 审中-公开
标题翻译：基于共享变量（SVB）的多核仿真同步方法
公开(公告)号：US20120233410A1
公开(公告)日：2012-09-13
申请号：US13046743
申请日：2011-03-13
申请人： Cheng-Yang FU , Meng-Huan Wu , Ren-Song Tsay
发明人： Cheng-Yang FU , Meng-Huan Wu , Ren-Song Tsay
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0837
摘要： The present invention discloses a shared-variable-based (SVB) approach for fast and accurate multi-core cache coherence simulation. While the intuitive, conventional approach, synchronizing at either every cycle or memory access, gives accurate simulation results, it has poor performance due to huge simulation overloads. In the present invention, timing synchronization is only needed before shared variable accesses in order to maintain accuracy while improving the efficiency in the proposed shared-variable-based approach.
摘要翻译：本发明公开了一种用于快速准确的多核高速缓存一致性模拟的共享变量（SVB）方法。虽然直观的常规方法，在每个周期或存储器访问同步，给出精确的模拟结果，由于巨大的模拟过载，它的性能不佳。在本发明中，仅在共享变量访问之前需要定时同步，以便在提出基于共享变量的方法中提高效率的同时保持准确性。

6. 发明申请

US20120197625A1 Data-dependency-Oriented Modeling Approach for Efficient Simulation of OS Preemptive Scheduling 审中-公开
标题翻译：基于数据依赖性的建模方法，用于高效地模拟OS抢占式调度
公开(公告)号：US20120197625A1
公开(公告)日：2012-08-02
申请号：US13016933
申请日：2011-01-28
申请人： Peng-Chih WANG , Meng-Huan Wu , Ren-Song Tsay
发明人： Peng-Chih WANG , Meng-Huan Wu , Ren-Song Tsay
IPC分类号： G06F9/45
CPC分类号： G06F9/485 , G06F17/5022
摘要： In the present disclosure, the DOM approach for the simulation of OS preemptive scheduling has presented and demonstrated. By maintaining the data-dependency between the software tasks, and guaranteeing the order of shared variable accesses, it can accurately simulate the preemption effect. Moreover, the proposed DOM OS model is implemented to enable preemptive scheduling in SystemC.
摘要翻译：在本公开中，用于模拟OS抢占式调度的DOM方法已经呈现并展示出来。通过维护软件任务之间的数据依赖关系，保证共享变量访问的顺序，可以准确模拟抢占效果。此外，提出的DOM OS模型被实现为在SystemC中启用抢占式调度。

7. 发明申请

US20120075159A1 ANTENNA MATCHING CIRCUIT CONTROL DEVICE 失效
标题翻译：天线匹配电路控制装置
公开(公告)号：US20120075159A1
公开(公告)日：2012-03-29
申请号：US13236033
申请日：2011-09-19
申请人： Chia-Hao CHANG , Meng-Huan Wu , Kuo-Chu Liao
发明人： Chia-Hao CHANG , Meng-Huan Wu , Kuo-Chu Liao
IPC分类号： H01Q1/50
CPC分类号： H01Q1/50 , H01Q1/24 , H03H7/38
摘要： The antenna matching circuit control device with an antenna body includes a sensing module, a processing module, a power adjusting module and a frequency adjusting module. The sensing module senses an object that approaches the antenna body and outputs a sensing signal accordingly. The processing module is coupled to the sensing module and outputs a first control signal and a second control signal according to the sensing signal. The power adjusting module is coupled to the processing module and controls a power amplifier to couple with one of a plurality of first matching circuits according to the first control signal. The frequency adjusting module is coupled to the antenna body and the power adjusting module. The frequency adjusting module controls one of a plurality of second matching circuits to couple with one of the first matching circuits according to the second control signal.
摘要翻译：具有天线体的天线匹配电路控制装置包括感测模块，处理模块，功率调整模块和频率调整模块。感测模块感测接近天线体的物体，并相应地输出感测信号。处理模块耦合到感测模块，并根据感测信号输出第一控制信号和第二控制信号。功率调节模块耦合到处理模块，并根据第一控制信号控制功率放大器与多个第一匹配电路之一耦合。频率调节模块耦合到天线体和功率调节模块。频率调整模块根据第二控制信号控制多个第二匹配电路中的一个与第一匹配电路之一耦合。

8. 发明授权

US09312600B2 Stylus and antenna thereof 有权
标题翻译：触针及其天线
公开(公告)号：US09312600B2
公开(公告)日：2016-04-12
申请号：US13775262
申请日：2013-02-25
申请人： Jen-Yu Wang , Wei-Cheng Lo , Yu-Chia Chang , Meng-Huan Wu , Chia-Hao Chang
发明人： Jen-Yu Wang , Wei-Cheng Lo , Yu-Chia Chang , Meng-Huan Wu , Chia-Hao Chang
IPC分类号： G06F3/033 , H01Q1/52 , G06F3/0354 , H01Q1/44 , H01Q9/04
CPC分类号： H01Q1/52 , G06F3/03545 , H01Q1/44 , H01Q9/0421
摘要： A stylus includes a conductive rod, a circuit board, and an antenna. The conductive rod has a first opening. The circuit board is disposed in the conductive rod and includes a ground portion, wherein the conductive rod is electrically connected to the ground portion. The antenna includes a radiating portion and a feeding portion. The feeding portion is electrically connected to the circuit board and extends to the outside of the conductive rod via the first opening. The radiating portion is disposed at the outside of the conductive rod and is electrically connected to the feeding portion.
摘要翻译：触针包括导电棒，电路板和天线。导电棒具有第一开口。电路板设置在导电棒中并且包括接地部分，其中导电棒电连接到接地部分。天线包括辐射部分和馈送部分。馈电部分电连接到电路板，并经由第一开口延伸到导电棒的外部。辐射部分设置在导电棒的外侧并与馈电部分电连接。

9. 发明授权

US08352924B2 Method and device for multi-core instruction-set simulation 有权
标题翻译：多核指令集仿真的方法和装置
公开(公告)号：US08352924B2
公开(公告)日：2013-01-08
申请号：US12588324
申请日：2009-10-13
申请人： Meng-Huan Wu , Cheng-Yang Fu , Peng-Chih Wang , Ren-Song Tsay
发明人： Meng-Huan Wu , Cheng-Yang Fu , Peng-Chih Wang , Ren-Song Tsay
IPC分类号： G06F9/45
CPC分类号： G06F17/5022 , G06F8/53 , G06F9/4552 , G06F2217/68
摘要： The present invention discloses a method for multi-core instruction-set simulation. The proposed method identifies the shared data segment and the dependency relationship between the different cores and thus effectively reduces the number of sync points and lowers the synchronization overhead, allowing multi-core instruction-set simulation to be performed more rapidly while ensuring that the simulation results are accurate. In addition, the present invention also discloses a device for multi-core instruction-set simulation.
摘要翻译：本发明公开了一种多核指令集仿真方法。所提出的方法识别共享数据段和不同核心之间的依赖关系，从而有效减少同步点数量，降低同步开销，从而允许更多地执行多核指令集仿真，同时确保仿真结果是准确的此外，本发明还公开了一种用于多核指令集仿真的装置。

10. 发明申请

US20110197174A1 Method, System and Computer Readable Medium for Generating Software Transaction-Level Modeling (TLM) Model 有权
标题翻译：用于生成软件事务级建模（TLM）模型的方法，系统和计算机可读介质
公开(公告)号：US20110197174A1
公开(公告)日：2011-08-11
申请号：US12701810
申请日：2010-02-08
申请人： Meng-Huan WU , Ren-Song Tsay
发明人： Meng-Huan WU , Ren-Song Tsay
IPC分类号： G06F9/45
CPC分类号： G06F8/53
摘要： The present invention discloses a system for generating a software TLM model, comprising a processing unit; a compiler coupled to the processing unit to generate target binary codes of a target software; a decompiler coupled to the processing unit to decompile the target binary codes into high level codes, for example C or C++ codes, to generate a functional model of the target software, wherein the functional model includes a plurality of basic blocks; an execution time calculating module coupled to the processing unit to calculate overall execution time of the plurality of the basic blocks of the functional model; a sync point identifying module coupled to the processing unit to identify sync points of the software transaction-level modeling model; and a time annotating module coupled to the processing unit to annotate the overall execution time of the basic blocks and the sync points into the functional model to obtain the software transaction-level modeling model.
摘要翻译：本发明公开了一种生成软件TLM模型的系统，包括处理单元; 耦合到所述处理单元以生成目标软件的目标二进制代码的编译器; 反编译器，其耦合到所述处理单元以将所述目标二进制代码反编译为高级代码，例如C或C ++代码，以生成所述目标软件的功能模型，其中所述功能模型包括多个基本块; 执行时间计算模块，耦合到所述处理单元，以计算所述功能模型的所述多个基本块的总执行时间; 耦合到所述处理单元的同步点识别模块，以识别所述软件交易级建模模型的同步点; 以及耦合到处理单元的时间注释模块，以将基本块和同步点的总体执行时间注释到功能模型中以获得软件事务级建模模型。

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