专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130054854A1 Full Bus Transaction Level Modeling Approach for Fast and Accurate Contention Analysis 审中-公开
标题翻译：完整的总线交易级建模方法，用于快速准确的竞争分析
公开(公告)号：US20130054854A1
公开(公告)日：2013-02-28
申请号：US13398083
申请日：2012-02-16
申请人： Mao-Lin Li , Chen-Kang Lo , Li-Chun Chen , Hong-Jie Huang , Jen-Chieh Yeh , Ren-Song Tsay
发明人： Mao-Lin Li , Chen-Kang Lo , Li-Chun Chen , Hong-Jie Huang , Jen-Chieh Yeh , Ren-Song Tsay
IPC分类号： G06F13/362
CPC分类号： G06F13/362 , G06F13/1642
摘要： The present invention presents an effective Cycle-count Accurate Transaction level (CCA-TLM) full bus modeling and simulation technique. Using the two-phase arbiter and master-slave models, an FSM-based Composite Master-Slave-pair and Arbiter Transaction (CMSAT) model is proposed for efficient and accurate dynamic simulations. This approach is particularly effective for bus architecture exploration and contention analysis of complex Multi-Processor System-on-Chip (MPSoC) designs.
摘要翻译：本发明提出了一种有效的循环计数精确交易级别（CCA-TLM）全总线建模和仿真技术。使用两相仲裁器和主从模型，提出了基于FSM的复合主从从对和仲裁器事务（CMSAT）模型，用于高效和准确的动态模拟。这种方法对于复杂的多处理器片上系统（MPSoC）设计的总线架构探索和竞争分析特别有效。

2. 发明申请

US20120144216A1 TRANSACTION LEVEL SYSTEM POWER ESTIMATION METHOD AND SYSTEM 有权
标题翻译：交易级系统功率估计方法与系统
公开(公告)号：US20120144216A1
公开(公告)日：2012-06-07
申请号：US13041443
申请日：2011-03-07
申请人： Wen-Tsan Hsieh , Jen-Chieh Yeh , Hong-Jie Huang , I-Yao Chuang
发明人： Wen-Tsan Hsieh , Jen-Chieh Yeh , Hong-Jie Huang , I-Yao Chuang
IPC分类号： G06F1/26
CPC分类号： G06F17/5022 , G06F17/504 , G06F17/5045 , G06F17/505 , G06F2217/78
摘要： A transaction level (TL) system power estimation method and system are provided. The method includes inserting at least a characteristic extractor into an electronic device of a target system. The characteristic extractor extracts at least a power characteristic of the electronic device when a TL simulation is proceeding. The power characteristic provided from the characteristic extractor is converted to at least a power consumption value by using a power model. The power consumption value is recorded into a power database, for analyzing power consumption of the whole target system. In some embodiments, the TL system power estimation method and system can be applied in the target system with dynamic power management. The TL system power estimation method and system also can be used with a high-level synthesizer to develop the power-aware electronic device in a short time.
摘要翻译：提供了交易级（TL）系统功率估计方法和系统。该方法包括至少将特征提取器插入到目标系统的电子设备中。当TL模拟正在进行时，特征提取器至少提取电子设备的功率特性。通过使用功率模型将从特征提取器提供的功率特性转换为至少功耗值。功耗值被记录在电力数据库中，用于分析整个目标系统的功耗。在一些实施例中，TL系统功率估计方法和系统可以应用于具有动态功率管理的目标系统中。 TL系统功率估计方法和系统也可以与高级合成器一起使用，以在短时间内开发功率感知电子设备。

3. 发明授权

US08510694B2 Transaction level system power estimation method and system 有权
标题翻译：交易级系统功率估算方法和系统
公开(公告)号：US08510694B2
公开(公告)日：2013-08-13
申请号：US13041443
申请日：2011-03-07
申请人： Wen-Tsan Hsieh , Jen-Chieh Yeh , Hong-Jie Huang , I-Yao Chuang
发明人： Wen-Tsan Hsieh , Jen-Chieh Yeh , Hong-Jie Huang , I-Yao Chuang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504 , G06F17/5045 , G06F17/505 , G06F2217/78
摘要： A transaction level (TL) system power estimation method and system are provided. The method includes inserting at least a characteristic extractor into an electronic device of a target system. The characteristic extractor extracts at least a power characteristic of the electronic device when a TL simulation is proceeding. The power characteristic provided from the characteristic extractor is converted to at least a power consumption value by using a power model. The power consumption value is recorded into a power database, for analyzing power consumption of the whole target system. In some embodiments, the TL system power estimation method and system can be applied in the target system with dynamic power management. The TL system power estimation method and system also can be used with a high-level synthesizer to develop the power-aware electronic device in a short time.
摘要翻译：提供了交易级（TL）系统功率估计方法和系统。该方法包括至少将特征提取器插入到目标系统的电子设备中。当TL模拟正在进行时，特征提取器至少提取电子设备的功率特性。通过使用功率模型将从特征提取器提供的功率特性转换为至少功耗值。功耗值被记录在电力数据库中，用于分析整个目标系统的功耗。在一些实施例中，TL系统功率估计方法和系统可以应用于具有动态功率管理的目标系统中。 TL系统功率估计方法和系统也可以与高级合成器一起使用，以在短时间内开发功率感知电子设备。

4. 发明申请

US20060156187A1 Method and apparatus for multiple polynomial-based random number generation 审中-公开
标题翻译：基于多项式的随机数生成方法和装置
公开(公告)号：US20060156187A1
公开(公告)日：2006-07-13
申请号：US11248250
申请日：2005-10-13
申请人： Cheng-Wen Wu , Jen-Chieh Yeh , Hung-hsun Ou
发明人： Cheng-Wen Wu , Jen-Chieh Yeh , Hung-hsun Ou
IPC分类号： H03M13/00
CPC分类号： G07C15/006 , G06F7/582
摘要： An apparatus for multiple polynomial-based random number generation includes an LUT device having a plurality of polynomials established therein, a signal selection unit coupled to the LUT device and operable so as to generate a select signal that is inputted to the LUT device to thereby select at least one of the polynomials established in the LUT device, and an LFSR device coupled to the LUT device and operable so as to perform LFSR operations based on the at least one of the polynomials selected from the LUT device. A method for multiple polynomial-based random number generation includes: a) establishing the polynomials in the LUT device, b) generating the select signal to select at least one of the polynomials, and c) enabling the LFSR device to perform the corresponding LFSR operations.
摘要翻译：一种用于多项式的多项式随机数生成装置，包括：具有多个多项式的LUT器件，其中建立了多个多项式;信号选择单元，耦合到LUT器件，并且可操作以产生输入到LUT器件的选择信号，从而选择在LUT设备中建立的多项式中的至少一个，以及耦合到LUT设备的LFSR设备，用于基于从LUT设备中选择的多项式中的至少一个执行LFSR操作。一种用于基于多项式的随机数生成方法包括：a）在LUT设备中建立多项式，b）产生选择信号以选择多项式中的至少一个，以及c）使LFSR设备能够执行相应的LFSR操作。

5. 发明申请

US20050140294A1 Cold cathode fluorescent lamp and method for forming the same 审中-公开
标题翻译：冷阴极荧光灯及其形成方法
公开(公告)号：US20050140294A1
公开(公告)日：2005-06-30
申请号：US11020123
申请日：2004-12-27
申请人： Ruey-Feng Jean , Jen-Chieh Yeh , Kuang-Lung Tsai , Shih-Hsien Lin
发明人： Ruey-Feng Jean , Jen-Chieh Yeh , Kuang-Lung Tsai , Shih-Hsien Lin
IPC分类号： H01J9/26 , H01J9/00 , H01J17/24 , H01J19/70 , H01J61/067 , H01J61/09 , H01J61/26 , H01J61/78
CPC分类号： H01J61/26 , H01J61/78
摘要： A cold cathode fluorescent lamp. The cold cathode fluorescent lamp includes a transparent tube, at least one absorptive structure and at least one absorptive layer. The transparent tube is filled with a gas including a material capable of arousing light by means, of an electric potential. The absorptive structure is disposed on one end of the transparent tube and includes a supporting mechanism having at least one opening. The absorptive layer is formed in the opening and is not filled with the opening.
摘要翻译：冷阴极荧光灯。冷阴极荧光灯包括透明管，至少一个吸收结构和至少一个吸收层。透明管充满包括能够通过电位引起光的材料的气体。吸收结构设置在透明管的一端，并且包括具有至少一个开口的支撑机构。吸收层形成在开口中，并且不填充开口。

6. 发明授权

US07065689B2 Diagonal testing method for flash memories 失效
标题翻译：闪存对角线测试方法
公开(公告)号：US07065689B2
公开(公告)日：2006-06-20
申请号：US10602377
申请日：2003-06-24
申请人： Sau-Kwo Chiu , Jen-Chieh Yeh , Kuo-Liang Cheng , Chih-Tsun Huang , Cheng-Wen Wu
发明人： Sau-Kwo Chiu , Jen-Chieh Yeh , Kuo-Liang Cheng , Chih-Tsun Huang , Cheng-Wen Wu
IPC分类号： G11C29/00 , G11C7/00 , G06F12/16
CPC分类号： G11C29/10 , G11C16/04
摘要： The present invention discloses a diagonal testing method for flash memories. The testing method regards the flash memory as several squares, and executes in the direction from top to bottom and from left to right. Each square is provided with a first diagonal in −45 degrees from the upper left to the lower right, and a second diagonal in +45 degrees from the lower left to the upper right. The present invention is to program the cells in the first diagonal or the second diagonal, and then read the cells except the first diagonal or the second diagonal; or, program the cells except the first diagonal or the second diagonal, and then read the cells in the first diagonal or the second diagonal so as to detect the disturb fault in the flash memories and normal memory fault models.
摘要翻译：本发明公开了一种闪存的对角线测试方法。测试方法将闪存存储为几个方格，并从上到下，从左到右的方向执行。每个正方形设有从左上到右下的-45度的第一个对角线，以及从左下到右上的+45度的第二个对角线。本发明是对第一对角线或第二对角线中的单元进行编程，然后读取第一对角线或第二对角线以外的单元; 或者，对第一对角线或第二对角线以外的单元进行编程，然后读取第一对角线或第二对角线中的单元，以便检测闪速存储器和正常存储器故障模型中的干扰故障。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式