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1. 发明申请

US20060195285A1 CANARY DEVICE FOR FAILURE ANALYSIS 失效
标题翻译：用于故障分析的CANARY设备
公开(公告)号：US20060195285A1
公开(公告)日：2006-08-31
申请号：US10906590
申请日：2005-02-25
申请人： Pierre Bouchard , Mark Hakey , Mark Masters , Leah Pastel , James Slinkman , David Vallett
发明人： Pierre Bouchard , Mark Hakey , Mark Masters , Leah Pastel , James Slinkman , David Vallett
IPC分类号： G06F19/00
CPC分类号： G01R31/2856 , G01R31/2831 , G01R31/318511 , G01R31/3187
摘要： A diagnostic system and method for testing an integrated circuit (IC) during fabrication thereof, wherein the diagnostic system comprises at least one IC chip comprising an electrical signature; a sacrificial circuit adjacent to the IC chip and comprising a known electrical signature and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the IC chip with the known electrical signature of the sacrificial circuit indicates that the IC chip is mis-designed. The diagnostic system further comprises a semiconductor wafer comprising a plurality of IC chips and a kerf area separating one IC chip from another IC chip. The sacrificial circuit is located in the kerf area or alternatively on each of the plurality of IC chips. A mis-designed IC chip comprises abnormally functioning circuitry.
摘要翻译：一种用于在其制造期间测试集成电路（IC）的诊断系统和方法，其中所述诊断系统包括至少一个包括电特征的IC芯片; 邻近于IC芯片的牺牲电路，包括已知的电气签名和故意错误设计的电路; 以及比较器，用于将IC芯片的电气签名与牺牲电路的已知电气签名进行比较，其中IC芯片的电子签名与牺牲电路的已知电气签名的匹配表明IC芯片是错误的设计。诊断系统还包括半导体晶片，其包括多个IC芯片和将IC芯片与另一IC芯片分开的切口区域。牺牲电路位于切口区域中，或者替代地位于多个IC芯片中的每一个上。错误设计的IC芯片包括异常功能的电路。

2. 发明申请

US20060038167A1 INTEGRATED CARBON NANOTUBE SENSORS 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US20060038167A1
公开(公告)日：2006-02-23
申请号：US10711083
申请日：2004-08-20
申请人： Mark Hakey , Mark Masters , Leah Pastel , David Vallett
发明人： Mark Hakey , Mark Masters , Leah Pastel , David Vallett
IPC分类号： H01L31/072
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

3. 发明申请

US20070197010A1 INTEGRATED CARBON NANOTUBE SENSORS 失效
标题翻译：集成碳纳米管传感器
公开(公告)号：US20070197010A1
公开(公告)日：2007-08-23
申请号：US11696370
申请日：2007-04-04
申请人： Mark Hakey , Mark Masters , Leah Pastel , David Vallett
发明人： Mark Hakey , Mark Masters , Leah Pastel , David Vallett
IPC分类号： H01L21/3205
CPC分类号： H01L29/0665 , B82Y10/00 , G01R31/2884 , H01L27/088 , H01L27/286 , H01L29/0673 , H01L29/78 , H01L51/0048 , H01L51/0512 , Y10S977/761 , Y10S977/762 , Y10S977/765
摘要： A method and structure for an integrated circuit comprising a first transistor and an embedded carbon nanotube field effect transistor (CNT FET) proximate to the first transistor, wherein the CNT FET is dimensioned smaller than the first transistor. The CNT FET is adapted to sense signals from the first transistor, wherein the signals comprise any of temperature, voltage, current, electric field, and magnetic field signals. Moreover, the CNT FET is adapted to measure stress and strain in the integrated circuit, wherein the stress and strain comprise any of mechanical and thermal stress and strain. Additionally, the CNT FET is adapted to detect defective circuits within the integrated circuit.
摘要翻译：一种集成电路的方法和结构，包括靠近第一晶体管的第一晶体管和嵌入式碳纳米管场效应晶体管（CNT FET），其中CNT FET的尺寸小于第一晶体管。 CNT FET适于感测来自第一晶体管的信号，其中信号包括温度，电压，电流，电场和磁场信号中的任何一个。此外，CNT FET适于测量集成电路中的应力和应变，其中应力和应变包括机械和热应力和应变中的任何一种。此外，CNT FET适用于检测集成电路内的故障电路。

4. 发明申请

US20050282297A1 METHOD AND STRUCTURE FOR DEFECT MONITORING OF SEMICONDUCTOR DEVICES USING POWER BUS WIRING GRIDS 失效
标题翻译：使用电力总线接线网的半导体器件缺陷监测的方法和结构
公开(公告)号：US20050282297A1
公开(公告)日：2005-12-22
申请号：US10710114
申请日：2004-06-18
申请人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
发明人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
IPC分类号： G01R31/28 , G01R31/307 , H01L21/00 , H01L23/544
CPC分类号： G01R31/2884 , G01R31/307 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.
摘要翻译：用于实现集成电路的缺陷检查的方法包括在第一金属互连级上配置电力总线栅格结构，所述电力总线栅格结构包括第一多个线对。第一组多个线对被布置成使得第一多个线对中的每一个中的第一线电耦合到第一金属互连水平面下方的导电结构，并且在第一多个线中的每一个中的第二线对最初与第一金属互连级别下方的导电结构电隔离。第一多个线对中的每一个中的第一线被偏置到已知电压，并且在第一多个线对中的每一个的第一线和第二线之间执行电荷对比度检查。

5. 发明申请

US20060232284A1 SENSOR DIFFERENTIATED FAULT ISOLATION 失效
标题翻译：传感器差异故障分离
公开(公告)号：US20060232284A1
公开(公告)日：2006-10-19
申请号：US10907787
申请日：2005-04-15
申请人： Kevin Condon , Theodore Levin , Leah Pastel , David Vallett
发明人： Kevin Condon , Theodore Levin , Leah Pastel , David Vallett
IPC分类号： G01R31/302
CPC分类号： G01R31/311 , G01R31/302 , G01R31/31728 , G01R31/3187
摘要： Disclosed is an apparatus and method for diagnostically testing circuitry within a device. The apparatus and method incorporate the use of energy (e.g., light, heat, magnetic, electric, etc.) applied directly to any location on the device that can affect the electrical activity within the circuitry being tested in order to produce an indicator of a response. A local sensor (e.g., photonic, magnetic, etc.) is positioned at another location on the device where the sensor can detect the indicator of the response within the circuitry. A correlator is configured with response location correlation software and/or circuit tracing software so that when the indicator is detected, the correlator can determine the exact location of a response causing a device failure and/or trace the connectivity of the circuitry, based upon the location of the energy source and the location of the sensor.
摘要翻译：公开了一种用于诊断测试设备内的电路的装置和方法。该装置和方法包括直接应用于设备上可能影响被测电路内的电活动的任何位置的能量（例如光，热，磁，电等）的使用，以便产生一个响应。本地传感器（例如，光子，磁性等）位于设备上的另一位置处，其中传感器可以检测电路内的响应的指示符。相关器被配置有响应位置相关软件和/或电路跟踪软件，使得当检测到指示符时，相关器可基于导致设备故障的确定位置和/或跟踪电路的连通性来确定电路的连接性能源的位置和传感器的位置。

6. 发明申请

US20060066342A1 Utilizing clock shield as defect monitor 失效
公开(公告)号：US20060066342A1
公开(公告)日：2006-03-30
申请号：US11280008
申请日：2005-11-16
申请人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
发明人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
IPC分类号： G01R31/26
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

7. 发明申请

US20060071208A1 INSPECTION METHODS AND STRUCTURES FOR VISUALIZING AND/OR DETECTING SPECIFIC CHIP STRUCTURES 有权
标题翻译：用于可视化和/或检测特定芯片结构的检查方法和结构
公开(公告)号：US20060071208A1
公开(公告)日：2006-04-06
申请号：US10711765
申请日：2004-10-04
申请人： Jerome Cann , Steven Holmes , Leendert Huisman , Cherie Kagan , Leah Pastel , Paul Pastel , James Salimeno , David Vallett
发明人： Jerome Cann , Steven Holmes , Leendert Huisman , Cherie Kagan , Leah Pastel , Paul Pastel , James Salimeno , David Vallett
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/76843 , H01L21/76865 , H01L21/7688
摘要： The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.
摘要翻译：本发明提供了用于促进特定芯片结构的可视化和/或检测的检查方法和结构。光学或荧光标记技术用于“污染”特定的芯片结构，以便于检测结构。此外，向半导体工艺中添加临时/牺牲照明（例如荧光）膜以便于检测特定的芯片结构。此外，在半导体工艺期间，用荧光材料掺杂特定的芯片结构。本发明的方法包括：提供第一和第二材料; 处理所述第一材料以形成半导体结构的一部分; 以及检测所述第二材料的状态以确定所述第一材料的处理是否完成。

8. 发明申请

US20070108964A1 UTILIZING CLOCK SHIELD AS DEFECT MONITOR 失效
标题翻译：使用时钟屏蔽作为缺陷监视器
公开(公告)号：US20070108964A1
公开(公告)日：2007-05-17
申请号：US11382601
申请日：2006-05-10
申请人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
发明人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译：公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。屏蔽与时钟信号接线相邻，接地线将屏蔽接地。屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

9. 发明申请

US20060026472A1 Designing Scan Chains With Specific Parameter Sensitivities to Identify Process Defects 失效
标题翻译：设计具有特定参数敏感度的扫描链来识别过程缺陷
公开(公告)号：US20060026472A1
公开(公告)日：2006-02-02
申请号：US10710642
申请日：2004-07-27
申请人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
发明人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

10. 发明申请

US20050285611A1 UTILIZING CLOCK SHIELD AS DEFECT MONITOR 有权
标题翻译：使用时钟屏蔽作为缺陷监视器
公开(公告)号：US20050285611A1
公开(公告)日：2005-12-29
申请号：US10710222
申请日：2004-06-28
申请人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
发明人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
IPC分类号： G01R31/02 , G01R31/26 , G01R31/30 , G01R31/317
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译：公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。屏蔽与时钟信号接线相邻，接地线将屏蔽接地。屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

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