专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4028694A A/D and D/A converter using C-2C ladder network 失效
标题翻译： A / D和D / A转换器采用C-2C梯形网络
公开(公告)号：US4028694A
公开(公告)日：1977-06-07
申请号：US585629
申请日：1975-06-10
申请人： Peter William Cook , Stanley E. Schuster
发明人： Peter William Cook , Stanley E. Schuster
IPC分类号： H03M1/74 , H01L21/822 , H01L27/04 , H01L27/08 , H03M1/00 , H03K13/02
CPC分类号： H01L27/0805 , H03M1/78 , H03M1/802
摘要： A C-2C analog-to digital and digital-to-analog converter is described, the C-2C designation referring to the arrangement of capacitance in a capacitor ladder network. The capacitors are formed in a monolithic, multilayer structure which includes a substrate, diffusion regions in the substrate, a polysilicon layer and an aluminum layer wherein the capacitances are formed between the aluminum layer and the polysilicon layer and between the polysilicon layer and the diffusion region, and these capacitances have the ratio of 2C to C respectively. The capacitor ladder network formed in the multilayer structure can be trimmed or adjusted electrically after manufacture to obtain the desired tolerances.
摘要翻译：描述了C-2C模拟到数字和数模转换器，C-2C指定是指电容梯形网络中电容的布置。电容器形成为单片多层结构，其包括衬底，衬底中的扩散区，多晶硅层和铝层，其中电容在铝层和多晶硅层之间以及多晶硅层和扩散区之间形成，这些电容分别具有2C与C的比例。在多层结构中形成的电容梯形网络可以在制造之后进行电动修整或调整以获得所需的公差。

2. 发明授权

US07821858B2 eDRAM hierarchical differential sense AMP 有权
标题翻译： eDRAM分层差分放大器
公开(公告)号：US07821858B2
公开(公告)日：2010-10-26
申请号：US12326143
申请日：2008-12-02
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C11/4097 , G11C11/4091
摘要： In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.
摘要翻译：在本发明的一个实施例中，实现了分级差分感测方法，其中1行DRAM单元的阵列以行和列组织，其中行表示字，并且列表示字的位，每个位列具有多于一个一对平衡的，真实的和补充的局部位线，局部位线通过CMOS晶体管开关连接到一对平衡的，真实的和补充的全局位线。

3. 发明授权

US07460423B2 Hierarchical 2T-DRAM with self-timed sensing 有权
标题翻译：具有自定时感测功能的分层2T-DRAM
公开(公告)号：US07460423B2
公开(公告)日：2008-12-02
申请号：US11620282
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C7/00 , G11C5/06 , G11C11/00
CPC分类号： G11C8/10 , G11C7/18 , G11C11/405 , G11C11/4076 , G11C11/4091 , G11C11/4097 , G11C2211/4013 , Y10T29/49002
摘要： An embodiment of the present invention is an array of 2 transistor DRAM cells organized in rows and columns in which the rows represent words and columns represent bits of the words, each bit column having a pair of balanced, true and complement bit lines, the bit lines being connected in a hierarchical bit line structure, comprising at least one local bit line pair and one global bit line pair, a sensing circuit connected to the global bit line pair detects a differential voltage transition on either line during a read access and provides a sensing strobe signal.
摘要翻译：本发明的实施例是以行和列组织的2个晶体管DRAM单元的阵列，其中行表示字和列表示字的位，每个位列具有一对平衡的，真和补码位线，该位线路以分层位线结构连接，包括至少一个本地位线对和一个全局位线对，连接到全局位线对的感测电路在读取访问期间检测任一行上的差分电压转换，并提供一个感应选通信号。

4. 发明授权

US07460387B2 eDRAM hierarchical differential sense amp 失效
标题翻译： eDRAM分层差分放大器
公开(公告)号：US07460387B2
公开(公告)日：2008-12-02
申请号：US11620328
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C5/06 , G11C11/24 , G11C7/00
CPC分类号： G11C11/4097 , G11C11/4091
摘要： In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.
摘要翻译：在本发明的一个实施例中，实现了分级差分感测方法，其中1行DRAM单元的阵列以行和列组织，其中行表示字，并且列表示字的位，每个位列具有多于一个一对平衡的，真实的和补充的局部位线，局部位线通过CMOS晶体管开关连接到一对平衡的，真实的和补充的全局位线。

5. 发明申请

US20080165561A1 HIERARCHICAL SIX-TRANSISTOR SRAM 有权
标题翻译：分层六极晶体管SRAM
公开(公告)号：US20080165561A1
公开(公告)日：2008-07-10
申请号：US11620297
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C5/06
CPC分类号： G11C11/412 , G11C11/413
摘要： An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing six devices, the storage nodes which store the true and complement of the data are constructed from a four device, cross coupled flip-flop cell, wherein one internal storage node of this cell is connected through an access pass gate to one local bit line (LBL), the second internal storage node connected in a like manner to a second LBL, each LBL connected to a limited number, e.g. 8 to 32 of other similar storage cells, the two LBLs each connected to the gate of a separate read head nFET for discharging to ground one of two previously precharged global read lines so as to pass the inverse of the signal on the LBL and thus on the read head gate to a global read/write bit line.
摘要翻译：本发明的实施例是一种SRAM存储器阵列，其包括具有每个单元包含六个器件的存储器单元，存储数据的真实和补码的存储节点由四个器件交叉耦合的触发器单元构成，其中一个内部该单元的存储节点通过访问传递门连接到一个本地位线（LBL），第二内部存储节点以类似的方式连接到第二LBL，每个LBL连接到有限数量，例如 8到32个其他类似的存储单元，两个LBL各自连接到单独的读头nFET的栅极，用于将两个先前预充电的全局读取线之一放电到地之上，以便通过LBL上的信号的反相，从而导通读头到全局读/写位线。

6. 发明授权

US07065665B2 Interlocked synchronous pipeline clock gating 有权
公开(公告)号：US07065665B2
公开(公告)日：2006-06-20
申请号：US10262769
申请日：2002-10-02
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： H04L5/00 , G06F9/30
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

7. 发明授权

US4618784A High-performance, high-density CMOS decoder/driver circuit 失效
标题翻译：高性能，高密度CMOS解码器/驱动电路
公开(公告)号：US4618784A
公开(公告)日：1986-10-21
申请号：US695664
申请日：1985-01-28
申请人： Barbara A. Chappell , Thekkemadathil V. Rajeevakumar , Stanley E. Schuster , Lewis M. Terman
发明人： Barbara A. Chappell , Thekkemadathil V. Rajeevakumar , Stanley E. Schuster , Lewis M. Terman
IPC分类号： H03K19/096 , G11C8/10 , G11C11/34 , G11C11/407 , G11C11/413 , G11C8/00 , H03K19/017 , H03K19/20
CPC分类号： G11C8/10
摘要： A decoder/driver circuit for a semiconductor momory having a A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the AN line is high. A driver circuit is connected to the selection means and is responsive to the output signal of the NOR decoder circuit and the first selection signal to provide an output signal on a first memory word line and is further responsive to the output signal of the NOR decoder circuit and the second selection signal to provide an output signal on a second memory word line.
摘要翻译：一种具有A1至AN（真）和A1至＆amp; upbar和A（补码）地址线的半导体器件的解码器/驱动器电路，用于从内部地址缓冲器向其接收A1至AN地址位信号。包括PHI PC线，用于在其上接收PHI PC预充电时钟信号，并且提供PHI R线用于在其上接收PHI R复位时钟信号。解码器/驱动器电路包括NOR解码器装置，其具有连接到用于AN到AN-1地址位的真和补地址线的A1至AN-1或A1至AN-1的多个晶体管开关装置，用于产生高电平或根据地址位状态在解码器输出节点上的低电平信号。解码器/驱动器电路还包括选择装置，其具有连接到解码器的输出节点的多个晶体管器件，以在解码器输出节点和AN线路为高电平时产生第一选择信号，并且当解码器输出时产生第二选择信号节点和＆upbar＆A线高。驱动器电路连接到选择装置，并且响应于NOR解码器电路的输出信号和第一选择信号，以在第一存储器字线上提供输出信号，并且还响应于NOR解码器电路的输出信号以及第二选择信号，以在第二存储器字线上提供输出信号。

8. 发明授权

US4491748A High performance FET driver circuit 失效
标题翻译：高性能FET驱动电路
公开(公告)号：US4491748A
公开(公告)日：1985-01-01
申请号：US254806
申请日：1981-04-16
申请人： Barbara A. Chappell , Stanley E. Schuster
发明人： Barbara A. Chappell , Stanley E. Schuster
IPC分类号： H03K5/02 , G11C8/00 , G11C8/08 , H03K17/04 , H03K17/06 , H03K17/687 , H03K19/017 , H03K19/096
CPC分类号： G11C8/08
摘要： An FET high performance driver circuit which is especially effective in an environment wherein both large input and output capacitive loads are present is described. The driver features a push-pull output circuit, a clocked load, and a switched transfer depletion FET adapted to decouple the large input capacitive load from an internal node of the driver circuit. This switched decoupling allows an isolation of the large input capacitance from the internal node, whereby the internal node potential can be raised rapidly, and the bootstrapping effectiveness at the internal node can be enhanced so as to significantly increase the circuit operating speed in driving large output capacitive loads.
摘要翻译：描述了在其中存在大的输入和输出电容性负载的环境中特别有效的FET高性能驱动器电路。驱动器具有推挽输出电路，时钟负载和切换传输耗尽FET，其适于将大输入电容性负载与驱动器电路的内部节点分离。这种开关去耦允许从内部节点隔离大的输入电容，从而可以快速提高内部节点电位，并且可以增强内部节点的自举效应，从而显着提高驱动大输出的电路工作速度电容负载

9. 发明授权

US07499312B2 Fast, stable, SRAM cell using seven devices and hierarchical bit/sense line 失效
标题翻译：快速，稳定的SRAM单元使用七个器件和分级位/检测线
公开(公告)号：US07499312B2
公开(公告)日：2009-03-03
申请号：US11620316
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C11/00 , G11C5/06
CPC分类号： G11C11/412 , G11C11/413
摘要： An embodiment of the present invention is an SRAM memory array comprising memory cells with each cell containing seven devices, wherein the basic storage nodes, which store the true and complement of the data, are constructed from six devices, forming a cross-coupled flip-flop cell. One internal storage node of this cell being connected to a separate read-pass device which passes the state of this node to a local bit line (LBL) for single-ended sensing, with the gate of this separate read-pass device connected to a separate read-word line.
摘要翻译：本发明的一个实施例是一种SRAM存储器阵列，其包括具有每个单元的存储器单元，所述存储器单元包含七个器件，其中存储数据的真实和补码的基本存储节点由六个器件构成，形成交叉耦合触发器，触发器电池。该单元的一个内部存储节点连接到单独的读通设备，该设备将该节点的状态传递到用于单端感测的本地位线（LBL），该单独的读通道设备的门连接到单独的读字线。

10. 发明申请

US20080165601A1 eDRAM HIERARCHICAL DIFFERENTIAL SENSE AMP 失效
标题翻译： eDRAM分层差分感测放大器
公开(公告)号：US20080165601A1
公开(公告)日：2008-07-10
申请号：US11620328
申请日：2007-01-05
申请人： Richard E. Matick , Stanley E. Schuster
发明人： Richard E. Matick , Stanley E. Schuster
IPC分类号： G11C7/00
CPC分类号： G11C11/4097 , G11C11/4091
摘要： In an embodiment of the present invention, a hierarchical differential sensing approach is effectuated wherein an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.
摘要翻译：在本发明的一个实施例中，实现了分级差分感测方法，其中1行DRAM单元的阵列以行和列组织，其中行表示字，并且列表示字的位，每个位列具有多于一个一对平衡的，真实的和补充的局部位线，局部位线通过CMOS晶体管开关连接到一对平衡的，真实的和补充的全局位线。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式