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1. 发明授权

US07709930B2 Tuneable semiconductor device with discontinuous portions in the sub-collector 失效
标题翻译：在子集电极中具有不连续部分的可调谐半导体器件
公开(公告)号：US07709930B2
公开(公告)日：2010-05-04
申请号：US11568156
申请日：2004-04-22
申请人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Gregory Freeman , Steven Voldman , Stephen A. St. Onge
发明人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Gregory Freeman , Steven Voldman , Stephen A. St. Onge
IPC分类号： H01L29/66
CPC分类号： H01L29/66363 , H01L29/0821 , H01L29/0834 , H01L29/66242 , H01L29/7378 , H01L29/74 , H01L29/861 , H01L29/872 , H01L29/93
摘要： Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.
摘要翻译：公开了一种形成半导体结构的方法，该半导体结构包括具有与下面的衬底不同的极性的不连续的非平面子集电极。此外，该结构包括在副集电极上方的有源区（集电极），有源区上方的基极和基极上方的发射极。不连续子集电极的不连续部分之间的距离调节了半导体结构的性能特性。可调谐的性能特点包括击穿电压，单位电流增益截止频率，单位功率增益截止频率，传输频率，电流密度，电容范围，噪声注入，少数载流子注入以及触发和保持电压。

2. 发明申请

US20070215978A1 TUNEABLE SEMICONDUCTOR DEVICE 失效
标题翻译：可调谐半导体器件
公开(公告)号：US20070215978A1
公开(公告)日：2007-09-20
申请号：US11568156
申请日：2004-04-22
申请人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Greg Freeman , Steven Voldman , Stephen Onge
发明人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Greg Freeman , Steven Voldman , Stephen Onge
IPC分类号： H01L29/66
CPC分类号： H01L29/66363 , H01L29/0821 , H01L29/0834 , H01L29/66242 , H01L29/7378 , H01L29/74 , H01L29/861 , H01L29/872 , H01L29/93
摘要： Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.
摘要翻译：公开了一种形成半导体结构的方法，该半导体结构包括具有与下面的衬底不同的极性的不连续的非平面子集电极。此外，该结构包括在副集电极上方的有源区（集电极），有源区上方的基极和基极上方的发射极。不连续子集电极的不连续部分之间的距离调节了半导体结构的性能特性。可调谐的性能特点包括击穿电压，单位电流增益截止频率，单位功率增益截止频率，传输频率，电流密度，电容范围，噪声注入，少数载流子注入以及触发和保持电压。

3. 发明申请

US20050225910A1 TUNABLE ESD TRIGGER AND POWER CLAMP CIRCUIT 失效
标题翻译： TUNABLE ESD触发器和电源钳位电路
公开(公告)号：US20050225910A1
公开(公告)日：2005-10-13
申请号：US10708911
申请日：2004-03-31
申请人： Andreas Stricker , Steven Voldman
发明人： Andreas Stricker , Steven Voldman
IPC分类号： H01L27/02 , H01L29/737 , H02H9/00
CPC分类号： H01L27/0259 , H01L29/7378 , H01L2924/0002 , H01L2924/00
摘要： A circuit and a method for the electrostatic discharge protection of integrated circuits. The electrostatic discharge protection circuit, including: an electrostatic discharge protection circuit, comprising: a first bipolar transistor coupled between a first circuit node and a second circuit node, the first bipolar transistor having a non-uniform subcollector region geometry, the first bipolar transistor having a different value for collector to emitter breakdown voltage than a value for collector to emitter breakdown voltage of an otherwise identical bipolar transistor having a uniform subcollector region geometry.
摘要翻译：集成电路的静电放电保护电路及方法。该静电放电保护电路包括：静电放电保护电路，包括：耦合在第一电路节点和第二电路节点之间的第一双极晶体管，所述第一双极晶体管具有不均匀的子集电极区域几何形状，所述第一双极晶体管具有相对于具有均匀子集电极区域几何形状的相同的双极晶体管的集电极至发射极击穿电压的值，集电极至发射极击穿电压的值不同。

4. 发明申请

US20060234484A1 METHOD AND STRUCTURE FOR ION IMPLANTATION BY ION SCATTERING 审中-公开
标题翻译：离子散射的离子注入方法和结构
公开(公告)号：US20060234484A1
公开(公告)日：2006-10-19
申请号：US10907752
申请日：2005-04-14
申请人： Louis Lanzerotti , David Sheridan , Steven Voldman
发明人： Louis Lanzerotti , David Sheridan , Steven Voldman
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L21/266 , H01L27/0259 , H01L29/66242 , H01L29/7378
摘要： A scatter-implant process and device is provided where a bi-level doping pattern is achieved in a single doping step. Additionally, devices having different breakdown voltages can be produced in a single implant process. The scatter-implant is fabricated by scattering implant ions off the edge of a mask, thereby reducing the ion energy causing the ions to doping shallower regions than the non-scattered ions which dope a lower region. By adjusting various parameters of the doping process such as, for example, ion type, ion energy, mask type and geometry, in a position of scattering edge relative to other structure of the device, the scatter-implant can be tuned to achieve certain properties of the semiconductor device. Additionally, circuits can be made using the scatter-implant process where pre-selected portion of the circuit incorporate the scatter-implant region and other portions of the circuit do not rely on the scatter region.
摘要翻译：提供散射注入工艺和器件，其中在单个掺杂步骤中实现双电平掺杂图案。另外，具有不同击穿电压的器件可以在单个注入工艺中产生。散射注入是通过将注入离子从掩模的边缘散射而制造的，从而减少了离子掺杂比掺杂较低区域的非散射离子更浅的区域的离子能。通过调整掺杂过程的各种参数，例如离子类型，离子能量，掩模类型和几何形状，在相对于器件的其他结构的散射边缘的位置，可以调整散射植入物以实现某些特性的半导体器件。另外，可以使用散射注入工艺制造电路，其中电路的预选部分包含散射注入区域，并且电路的其它部分不依赖于散射区域。

5. 发明申请

US20080201677A1 Integrated Circuit (IC) Chip Input/Output (I/O) Cell Design Optimization Method And IC chip With Optimized I/O Cells 审中-公开
标题翻译：集成电路（IC）芯片输入/输出（I / O）单元设计优化方法和具有优化I / O单元的IC芯片
公开(公告)号：US20080201677A1
公开(公告)日：2008-08-21
申请号：US11677136
申请日：2007-02-21
申请人： Faye Baker , Albert M. Chu , Wai Ling Chung-Maloney , Steven Voldman
发明人： Faye Baker , Albert M. Chu , Wai Ling Chung-Maloney , Steven Voldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , H01L22/20 , H01L2924/0002 , H01L2924/014 , Y02P90/265 , H01L2924/00
摘要： A method of fabricating an integrated circuit (IC) chip. A standard cell macro (e.g., an Off Chip Interface (OCI) cell) is defined with circuit elements identified as in a macro domain. A variable macro boundary is defined for the standard cell macro. Shapes are selectively added to design layers in the macro boundary to occupy existing white space. Each supplemented layer is checked for technology rules violations in the macro boundary. Each layer is also checked for known sensitivities in the macro boundary.
摘要翻译：一种制造集成电路（IC）芯片的方法。使用在宏域中标识的电路元件来定义标准单元宏（例如，离散芯片接口（OCI）单元）。为标准单元格宏定义了可变宏边界。形状被选择性地添加到宏边界中的设计层以占据现有的空白。检查每个补充层在宏观边界违反技术规则。还检查每个层在宏观边界中的已知敏感度。

6. 发明申请

US20080036029A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20080036029A1
公开(公告)日：2008-02-14
申请号：US11870567
申请日：2007-10-11
申请人： Xuefeng LIU , Rober Rassel , Steven Voldman
发明人： Xuefeng LIU , Rober Rassel , Steven Voldman
IPC分类号： H01L29/00
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/7378
摘要： A design structure embodied in a machine readable medium used in a design process. The design structure includes a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer, and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The design structure additionally includes a reach-through structure connecting the first and second sub-collectors, and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. Also, the design structure includes N+ diffusion regions in contact with the N-well, a P+ diffusion region within the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
摘要翻译：在设计过程中使用的机器可读介质中体现的设计结构。该设计结构包括形成在衬底的上部和第一外延层的下部的第一子集电极和形成在第一外延层的上部中的第二子集电极，外延层。该设计结构还包括连接第一和第二子集电器的通孔结构以及形成在第二外延层的一部分中并与第二子集电极和达到通孔结构接触的N阱。此外，设计结构包括与N阱接触的N +扩散区域，N阱内的P +扩散区域和N +和P +扩散区域之间的浅沟槽隔离结构。

7. 发明申请

US20060273372A1 LATERAL LUBISTOR STRUCTURE AND METHOD 有权
标题翻译：侧向劳工组织结构与方法
公开(公告)号：US20060273372A1
公开(公告)日：2006-12-07
申请号：US10908961
申请日：2005-06-02
申请人： Steven Voldman , Jack Mandelman
发明人： Steven Voldman , Jack Mandelman
IPC分类号： H01L27/108
CPC分类号： H01L29/7391 , H01L27/0248 , H01L27/1203 , H01L29/785 , H01L2029/7857
摘要： An ESD LUBISTOR structure based on FINFET technology employs a vertical fin (a thin vertical member containing the source, drain and body of the device) in alternatives with and without a gate. The gate may be connected to the external electrode being protected to make a self-activating device or may be connected to a reference voltage. The device may be used in digital or analog circuits.
摘要翻译：基于FINFET技术的ESD LUBISTOR结构在具有和不具有栅极的情况下采用垂直翅片（包含装置的源极，漏极和主体的薄垂直构件）。栅极可以连接到受保护的外部电极以形成自激活装置或者可以连接到参考电压。该器件可用于数字或模拟电路。

8. 发明申请

US20060246682A1 PRODUCT AND METHOD FOR INTEGRATION OF DEEP TRENCH MESH AND STRUCTURES UNDER A BOND PAD 失效
标题翻译：产品和方法，用于整合深层沥青网和结构桩
公开(公告)号：US20060246682A1
公开(公告)日：2006-11-02
申请号：US10908118
申请日：2005-04-28
申请人： Ephrem Gebreselasie , William Motsiff , Wolfgang Sauter , Steven Voldman
发明人： Ephrem Gebreselasie , William Motsiff , Wolfgang Sauter , Steven Voldman
IPC分类号： H01L21/76
CPC分类号： H01L27/0207 , H01L21/76224 , H01L21/823481 , H01L21/8249 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A method of integrating circuit components under bond pads includes establishing a trench border on a circuit element and synthesizing a set of trench mesh edges of a trench mesh to be coincident with the trench border on the circuit element. The method further includes eliminating a trench mesh contained within the trench border of the trench circuit element.
摘要翻译：将电路部件集成在接合焊盘下面的方法包括在电路元件上建立沟槽边界，并且合成沟槽网格的一组沟槽网格边缘以与电路元件上的沟槽边界重合。该方法还包括消除包含在沟槽电路元件的沟槽边界内的沟槽网格。

9. 发明申请

US20060110909A1 DENDRITE GROWTH CONTROL CIRCUIT 有权
公开(公告)号：US20060110909A1
公开(公告)日：2006-05-25
申请号：US10904680
申请日：2004-11-23
申请人： Douglas Hershberger , Steven Voldman , Michael Zierak
发明人： Douglas Hershberger , Steven Voldman , Michael Zierak
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838
摘要： A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device.

10. 发明申请

US20050283265A1 OPTIMIZED SCHEDULING BASED ON SENSITIVITY DATA 有权
标题翻译：基于敏感性数据的优化调度
公开(公告)号：US20050283265A1
公开(公告)日：2005-12-22
申请号：US10710065
申请日：2004-06-16
申请人： Brian Denton , Cuc Huynh , Shreesh Tandel , Steven Voldman
发明人： Brian Denton , Cuc Huynh , Shreesh Tandel , Steven Voldman
IPC分类号： G06F19/00
CPC分类号： G06Q10/06
摘要： A scheduling optimizer system, method and program product that analyzes a device for sensitivities, such as ESD sensitivities, and allows for modification of a floor schedule of the assembly unit of the device based on the sensitivity of the device while improving the overall performance of the assembly unit are disclosed. The scheduling optimizer analyzes sensitivity data for a device during operation of the assembly unit on the floor schedule. The floor schedule is then optimized based on the analyzed sensitivity data.
摘要翻译：调度优化器系统，方法和程序产品，用于分析设备的灵敏度，如ESD灵敏度，并允许基于设备的灵敏度修改设备的组装单元的楼层调度，同时提高整体性能公开了组装单元。调度优化器根据楼层进度分析装配单元运行期间设备的灵敏度数据。然后根据分析的灵敏度数据优化楼层进度。

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