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1. 发明申请

US20130075821A1 Semiconductor Device Comprising Replacement Gate Electrode Structures and Self-Aligned Contact Elements Formed by a Late Contact Fill 有权
标题翻译：包括替代栅极电极结构的半导体器件和由晚接触填料形成的自对准接触元件
公开(公告)号：US20130075821A1
公开(公告)日：2013-03-28
申请号：US13241915
申请日：2011-09-23
申请人： Peter Baars , Richard Carter , Rolf Stephan
发明人： Peter Baars , Richard Carter , Rolf Stephan
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/76814 , H01L29/66545 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material.
摘要翻译：当在基于更换栅极方法的高k金属栅电极结构的复杂半导体器件中形成自对准接触元件时，自对准接触开口用适当的填充材料填充，例如多晶硅而栅电极结构基于可相对于牺牲填充材料以高选择性去除的占位符材料提供。以这种方式，高k金属栅电极结构可以在去除牺牲填充材料之前用适当的接触材料实际填充接触开口之前完成。在一个说明性实施例中，栅电极结构的占位符材料以硅/锗材料的形式提供。

2. 发明授权

US08846513B2 Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill 有权
标题翻译：半导体器件包括替代栅电极结构和由后接触填充形成的自对准接触元件
公开(公告)号：US08846513B2
公开(公告)日：2014-09-30
申请号：US13241915
申请日：2011-09-23
申请人： Peter Baars , Richard Carter , Rolf Stephan
发明人： Peter Baars , Richard Carter , Rolf Stephan
IPC分类号： H01L21/3205 , H01L21/768 , H01L29/66 , H01L21/285 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/28518 , H01L21/76814 , H01L29/66545 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： When forming self-aligned contact elements in sophisticated semiconductor devices in which high-k metal gate electrode structures are to be provided on the basis of a replacement gate approach, the self-aligned contact openings are filled with an appropriate fill material, such as polysilicon, while the gate electrode structures are provided on the basis of a placeholder material that can be removed with high selectivity with respect to the sacrificial fill material. In this manner, the high-k metal gate electrode structures may be completed prior to actually filling the contact openings with an appropriate contact material after the removal of the sacrificial fill material. In one illustrative embodiment, the placeholder material of the gate electrode structures is provided in the form of a silicon/germanium material.
摘要翻译：当在基于更换栅极方法的高k金属栅电极结构的复杂半导体器件中形成自对准接触元件时，自对准接触开口用适当的填充材料填充，例如多晶硅而栅电极结构基于可相对于牺牲填充材料以高选择性去除的占位符材料提供。以这种方式，高k金属栅电极结构可以在去除牺牲填充材料之前用适当的接触材料实际填充接触开口之前完成。在一个说明性实施例中，栅电极结构的占位符材料以硅/锗材料的形式提供。

3. 发明授权

US08835245B2 Semiconductor device comprising self-aligned contact elements 有权
标题翻译：包括自对准接触元件的半导体器件
公开(公告)号：US08835245B2
公开(公告)日：2014-09-16
申请号：US13372604
申请日：2012-02-14
申请人： Peter Baars , Till Schloesser , Frank Jakubowski , Andy Wei , Richard Carter , Matthias Schaller
发明人： Peter Baars , Till Schloesser , Frank Jakubowski , Andy Wei , Richard Carter , Matthias Schaller
IPC分类号： H01L21/8234 , H01L21/768 , H01L21/285 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823475 , H01L21/28518 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L21/823437 , H01L29/66636 , H01L29/7848
摘要： When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.
摘要翻译：当形成复杂的半导体器件时，可以在替换栅电极结构的占位符材料之前形成自对准触点，将替代栅极方法与自对准的接触方式结合使用。

4. 发明授权

US08647952B2 Encapsulation of closely spaced gate electrode structures 有权
标题翻译：密封间隔栅电极结构的封装
公开(公告)号：US08647952B2
公开(公告)日：2014-02-11
申请号：US12974037
申请日：2010-12-21
申请人： Peter Baars , Richard Carter , Andy Wei
发明人： Peter Baars , Richard Carter , Andy Wei
IPC分类号： H01L21/336
CPC分类号： H01L27/092 , H01L21/28512 , H01L21/823412 , H01L21/823425 , H01L21/823475 , H01L23/28 , H01L23/485 , H01L29/6656 , H01L29/66628 , H01L29/7834 , H01L29/7847 , H01L2924/0002 , H01L2924/00
摘要： Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.
摘要翻译：通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中相邻栅电极之间的间距被积极地缩放，并且其中可以利用自对准接触元件来避免通常与使用通常可获得的光刻技术形成的窄接触元件。一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构，然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤，随后在第二层上形成第三电介质材料的第三层，其中形成第三层还包括形成第一水平部分在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。

5. 发明申请

US20120211808A1 FIN-TRANSISTOR FORMED ON A PATTERNED STI REGION BY LATE FIN ETCH 有权
标题翻译： FIN-TRANSISTOR通过最新的FIN ETCH形成在图案区域
公开(公告)号：US20120211808A1
公开(公告)日：2012-08-23
申请号：US13372837
申请日：2012-02-14
申请人： Andy Wei , Peter Baars , Richard Carter , Frank Ludwig
发明人： Andy Wei , Peter Baars , Richard Carter , Frank Ludwig
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823425 , H01L21/823431 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L29/1045 , H01L29/165 , H01L29/41783 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/66575 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.
摘要翻译：当形成复杂的半导体器件时，与平面晶体管组合的三维晶体管可以通过在早期制造阶段中形成半导体翅片（即，在形成浅沟槽隔离时）基于替代栅极接近和自对准接触元件而形成其中半导体翅片的最终电有效高度可以在提供自对准接触元件之后和在更换栅极接近期间被调整。

6. 发明授权

US08357978B1 Methods of forming semiconductor devices with replacement gate structures 有权
标题翻译：用替换栅极结构形成半导体器件的方法
公开(公告)号：US08357978B1
公开(公告)日：2013-01-22
申请号：US13230360
申请日：2011-09-12
申请人： Peter Baars , Andy Wei , Richard Carter
发明人： Peter Baars , Andy Wei , Richard Carter
IPC分类号： H01L21/70 , H01L29/76 , H01L21/8238 , H01L21/8234 , H01L21/336
CPC分类号： H01L27/088 , H01L21/76897 , H01L21/823828 , H01L21/823871 , H01L23/485 , H01L29/4966 , H01L29/66545 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein are various methods of forming replacement gate structures on semiconductor devices and devices incorporating such gate structures. In one example, the device includes a plurality of gate structures and at least one sidewall spacer positioned proximate each of the gate structures, a metal silicide region in a source/drain region formed in a substrate, wherein the metal silicide region extend laterally so as to contact the sidewall spacer positioned proximate each of the gate structures and a conductive contact positioned between the gate structures that conductively contacts the metal silicide region, wherein the conductive contact has a bottom portion that is wider than an upper portion of the conductive contact.
摘要翻译：这里公开了在半导体器件上形成替代栅极结构和结合这种栅极结构的器件的各种方法。在一个示例中，该器件包括多个栅极结构和位于每个栅极结构附近的至少一个侧壁间隔物，在基底中形成的源极/漏极区中的金属硅化物区域，其中金属硅化物区域横向延伸以便接触定位在每个栅极结构附近的侧壁隔离物和位于导电接触金属硅化物区域的栅极结构之间的导电接触，其中导电接触件具有比导电接触件的上部更宽的底部部分。

7. 发明申请

US20120211837A1 SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS 有权
标题翻译：包含自对准接触元件的半导体器件
公开(公告)号：US20120211837A1
公开(公告)日：2012-08-23
申请号：US13372604
申请日：2012-02-14
申请人： Peter Baars , Till Schloesser , Frank Jakubowski , Andy Wei , Richard Carter , Matthias Schaller
发明人： Peter Baars , Till Schloesser , Frank Jakubowski , Andy Wei , Richard Carter , Matthias Schaller
IPC分类号： H01L21/28 , H01L21/283 , H01L27/088
CPC分类号： H01L21/823475 , H01L21/28518 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L21/823437 , H01L29/66636 , H01L29/7848
摘要： When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures.
摘要翻译：当形成复杂的半导体器件时，可以在替换栅极电极结构的占位符材料之前形成自对准触点，将替代栅极方法与自对准接触方式结合使用。

8. 发明申请

US20120153398A1 Encapsulation of Closely Spaced Gate Electrode Structures 有权
标题翻译：密封栅电极结构的封装
公开(公告)号：US20120153398A1
公开(公告)日：2012-06-21
申请号：US12974037
申请日：2010-12-21
申请人： Peter Baars , Richard Carter , Andy Wei
发明人： Peter Baars , Richard Carter , Andy Wei
IPC分类号： H01L27/092 , H01L21/8234 , H01L29/772 , H01L21/28
CPC分类号： H01L27/092 , H01L21/28512 , H01L21/823412 , H01L21/823425 , H01L21/823475 , H01L23/28 , H01L23/485 , H01L29/6656 , H01L29/66628 , H01L29/7834 , H01L29/7847 , H01L2924/0002 , H01L2924/00
摘要： Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein the pitch between adjacent gate electrodes is aggressively scaled, and wherein self-aligning contact elements may be utilized to avoid the high electrical resistance levels commonly associated with narrow contact elements formed using typically available photolithography techniques. One illustrative embodiment includes forming first and second gate electrode structures above a semiconductor substrate, then forming a first layer of a first dielectric material adjacent to or in contact with the sidewalls of each of the first and second gate electrode structures. The illustrative method further includes a step of forming a second layer of a second dielectric material on the first layer, followed by forming a third layer of a third dielectric material on the second layer, wherein forming the third layer further comprises forming a first horizontal portion of the third layer above a surface of the semiconductor substrate between the first and second gate electrode structures.
摘要翻译：通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中相邻栅电极之间的间距被积极地缩放，并且其中可以利用自对准接触元件来避免通常与使用通常可获得的光刻技术形成的窄接触元件。一个说明性实施例包括在半导体衬底之上形成第一和第二栅电极结构，然后形成与第一和第二栅电极结构中的每一个的侧壁相邻或接触的第一电介质材料的第一层。说明性方法还包括在第一层上形成第二电介质材料的第二层的步骤，随后在第二层上形成第三电介质材料的第三层，其中形成第三层还包括形成第一水平部分在第一和第二栅电极结构之间的半导体衬底的表面上方的第三层。

9. 发明授权

US08652889B2 Fin-transistor formed on a patterned STI region by late fin etch 有权
标题翻译：通过后鳍蚀刻形成在图案化STI区上的鳍状晶体管
公开(公告)号：US08652889B2
公开(公告)日：2014-02-18
申请号：US13372837
申请日：2012-02-14
申请人： Andy Wei , Peter Baars , Richard Carter , Frank Ludwig
发明人： Andy Wei , Peter Baars , Richard Carter , Frank Ludwig
IPC分类号： H01L21/84 , H01L27/12 , H01L29/66
CPC分类号： H01L21/823807 , H01L21/823412 , H01L21/823425 , H01L21/823431 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L29/1045 , H01L29/165 , H01L29/41783 , H01L29/665 , H01L29/66537 , H01L29/66545 , H01L29/66575 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.
摘要翻译：当形成复杂的半导体器件时，与平面晶体管组合的三维晶体管可以通过在早期制造阶段中形成半导体翅片（即，在形成浅沟槽隔离时）基于替代栅极接近和自对准接触元件而形成其中半导体翅片的最终电有效高度可以在提供自对准接触元件之后和在更换栅极接近期间被调整。

10. 发明授权

US08853810B2 Integrated circuits that include deep trench capacitors and methods for their fabrication 有权
标题翻译：集成电路包括深沟槽电容器及其制造方法
公开(公告)号：US08853810B2
公开(公告)日：2014-10-07
申请号：US13218262
申请日：2011-08-25
申请人： Peter Baars , Till Schloesser
发明人： Peter Baars , Till Schloesser
IPC分类号： H01L27/108 , H01L21/8242 , H01L27/12 , H01L21/84 , H01L27/02 , H01L49/02
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/1087 , H01L27/1203 , H01L28/91
摘要： Methods are provided for fabricating an integrated circuit that includes a deep trench capacitor. One method includes fabricating a plurality of transistors on a semiconductor substrate, the plurality of transistors each including gate structures, source and drain regions, and silicide contacts to the source and drain regions. A trench is then etched into the semiconductor substrate in proximity to the drain region of a selected transistor. The trench is filled with a layer of metal in contact with the semiconductor substrate, a layer of dielectric material overlying the layer of metal, and a second metal overlying the layer of dielectric material. A metal contact is then formed coupling the second metal to the silicide contact on the drain region of the selected transistor. A bit line is formed contacting the source region of the selected transistor and a word line is formed contacting the gate structure of the transistor.
摘要翻译：提供了用于制造包括深沟槽电容器的集成电路的方法。一种方法包括在半导体衬底上制造多个晶体管，所述多个晶体管各自包括栅极结构，源极和漏极区以及到源极和漏极区的硅化物接触。然后在所选择的晶体管的漏极区域附近将沟槽蚀刻到半导体衬底中。沟槽填充有与半导体衬底接触的金属层，覆盖金属层的电介质材料层和覆盖在介电材料层上的第二金属。然后形成金属接触，将第二金属耦合到所选晶体管的漏极区上的硅化物接触。与所选择的晶体管的源极区域接触的位线形成为与晶体管的栅极结构接触的字线。

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