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1. 发明授权

US06420225B1 Method of fabricating power rectifier device 有权
标题翻译：电力整流装置的制造方法
公开(公告)号：US06420225B1
公开(公告)日：2002-07-16
申请号：US09805815
申请日：2001-03-13
申请人： Paul Chang , Vladimir Rodov , Geeng-Chuan Chern , Charles Lin , Ching-Lang Chiang
发明人： Paul Chang , Vladimir Rodov , Geeng-Chuan Chern , Charles Lin , Ching-Lang Chiang
IPC分类号： H01L218234
CPC分类号： H01L29/7802 , H01L21/2815 , H01L27/0727 , H01L27/0814 , H01L27/095 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/66356 , H01L29/66712 , H01L29/781 , H01L29/861
摘要： A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate.
摘要翻译：一种垂直半导体整流器件包括第一导电类型的半导体衬底，并且具有绝缘地形成在第一主表面上的多个栅极和在第一导电类型的第一导电类型的表面区域中形成的多个第一导电类型的源极/漏极区域主要表面毗邻门。第二导电类型的多个通道各自邻接源/漏区并在栅极下方延伸。

2. 发明授权

US06743703B2 Power diode having improved on resistance and breakdown voltage 有权
标题翻译：功率二极管具有改善的导通电阻和击穿电压
公开(公告)号：US06743703B2
公开(公告)日：2004-06-01
申请号：US10238104
申请日：2002-09-09
申请人： Vladimir Rodov , Paul Chang , Jianren Bao , Wayne Y. W. Hsueh , Arthur Ching-Lang Chiang , Geeng-Chuan Chern
发明人： Vladimir Rodov , Paul Chang , Jianren Bao , Wayne Y. W. Hsueh , Arthur Ching-Lang Chiang , Geeng-Chuan Chern
IPC分类号： H01L2974
CPC分类号： H01L29/7802 , H01L21/2815 , H01L27/0727 , H01L27/0814 , H01L27/095 , H01L29/0619 , H01L29/0634 , H01L29/1095 , H01L29/66712 , H01L29/781 , H01L29/861 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A two-terminal power diode has improved reverse bias breakdown voltage and on resistance includes a semiconductor body having two opposing surfaces and a superjunction structure therebetween, the superjunction structure including a plurality of alternating P and N doped regions aligned generally perpendicular to the two surfaces. The P and N doped regions can be parallel stripes or a mesh with each region being surrounded by doped material of opposite conductivity type. A diode junction associated with one surface can be an anode region with a gate controlled channel region connecting the anode region to the superjunction structure. Alternatively, the diode junction can comprise a metal forming a Schottky junction with the one surface. The superjunction structure is within the cathode and spaced from the anode. The spacing can be varied during device fabrication.
摘要翻译：双端功率二极管具有改进的反向偏压击穿电压，并且导通电阻包括具有两个相对表面的半导体本体和它们之间的超结结构，所述超结结构包括多个交替的P和N掺杂区域，其大致垂直于两个表面排列。 P和N掺杂区域可以是平行条纹或网状物，每个区域被相反导电类型的掺杂材料包围。与一个表面相关联的二极管结可以是具有将阳极区域连接到超结构结构的栅极控制沟道区域的阳极区域。或者，二极管结可以包括与该表面形成肖特基结的金属。超结构在阴极内并与阳极间隔开。间隔可以在器件制造过程中变化。

3. 发明授权

US06515330B1 Power device having vertical current path with enhanced pinch-off for current limiting 失效
标题翻译：具有垂直电流路径的功率器件，具有增强的夹断电流限制
公开(公告)号：US06515330B1
公开(公告)日：2003-02-04
申请号：US10037495
申请日：2002-01-02
申请人： Gary M. Hurtz , Vladimir Rodov , Geeng-Chuan Chern , Paul Chang , Ching-Lang Chiang
发明人： Gary M. Hurtz , Vladimir Rodov , Geeng-Chuan Chern , Paul Chang , Ching-Lang Chiang
IPC分类号： H01L2976
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/1095 , H01L29/66712 , H01L29/7802 , H01L29/861
摘要： A semiconductor current limiting device is provided by a two-terminal vertical N(P)-channel MOSFET device having the gate, body, and source terminals tied together as the anode and the drain terminal as the cathode. The doping profile of the body is so tailored with ion implantation that a depletion region pinches off to limit current. The body comprises a shallow implant to form a MOS channel and an additional deep implant through a spacer shielding the channel area. Implanted a higher energies and at an acute angle, the deep implant protrudes into the regular current path of the vertical MOSFET.
摘要翻译：半导体限流器件由两端垂直N（P）沟道MOSFET器件提供，其栅极，体和源极端子连接在一起作为阳极，漏极端子作为阴极。使用离子注入来定制主体的掺杂特性，耗尽区夹紧以限制电流。主体包括浅植入物以形成MOS通道，并通过隔离屏蔽通道区域的间隔物进行额外的深度注入。注入较高的能量并且以锐角，深的注入突出到垂直MOSFET的常规电流通路中。

4. 发明授权

US06765264B1 Method of fabricating power rectifier device to vary operating parameters and resulting device 有权
标题翻译：制造动力整流装置以改变运行参数和产生的装置的方法
公开(公告)号：US06765264B1
公开(公告)日：2004-07-20
申请号：US10446246
申请日：2003-05-27
申请人： Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Vladimir Rodov , Charles Lin
发明人： Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Vladimir Rodov , Charles Lin
IPC分类号： H01L2976
CPC分类号： H01L29/861 , H01L21/2815 , H01L29/0696 , H01L29/6609 , H01L29/7802
摘要： A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction sepcarating the channel region from the substrate of first conductivity type, In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.
摘要翻译：一种垂直半导体整流器件包括第一导电类型的半导体衬底，并且具有绝缘地形成在第一主表面上的多个栅极和在第一导电类型的第一导电类型的表面区域中形成的多个第一导电类型的源极/漏极区域主要表面毗邻门。第二导电类型的多个通道每个都邻接源极/漏极区并且在栅极下方延伸，每个沟道横向渐变，其中倾斜的PN结从第一导电类型的衬底分离沟道区。在制造垂直半导体整流器在半导体的表面上形成部分离子掩模，其掩模具有倾斜表面，该倾斜表面改变通过掩模的离子的路径长度，以形成横向渐变的通道区域。

5. 发明授权

US06624030B2 Method of fabricating power rectifier device having a laterally graded P-N junction for a channel region 有权
标题翻译：制造具有用于沟道区域的横向渐变的P-N结的功率整流装置的方法
公开(公告)号：US06624030B2
公开(公告)日：2003-09-23
申请号：US09742262
申请日：2000-12-19
申请人： Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Vladimir Rodov , Charles Lin
发明人： Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Vladimir Rodov , Charles Lin
IPC分类号： H01L21336
CPC分类号： H01L29/861 , H01L21/2815 , H01L29/0696 , H01L29/6609 , H01L29/7802
摘要： A vertical semiconductor rectifier device includes a semiconductor substrate of first conductivity type and having a plurality of gates insulatively formed on a first major surface and a plurality of source/drain regions of the first conductivity type formed in surface regions of second conductivity type in the first major surface adjacent to the gates. A plurality of channels of the second conductivity type each abuts a source/drain region and extends under a gate, each channel being laterally graded with a sloped P-N junction separating the channel region from the substrate of first conductivity type. In fabricating the vertical semiconductor rectifier device, a partial ion mask is formed on the surface of the semiconductor with the mask having a sloped surface which varies the path length of ions through the mask to form laterally-graded channel regions.
摘要翻译：一种垂直半导体整流器件包括第一导电类型的半导体衬底，并且具有绝缘地形成在第一主表面上的多个栅极和在第一导电类型的第一导电类型的表面区域中形成的多个第一导电类型的源极/漏极区域主要表面毗邻门。第二导电类型的多个通道每个都邻接源极/漏极区并在栅极下方延伸，每个沟道横向渐变，其中沟道区域与第一导电类型的衬底分离出倾斜的P-N结。在制造垂直半导体整流器件时，在半导体表面上形成一个部分离子掩模，该掩模具有倾斜表面，该倾斜表面改变通过该掩模的离子的路径长度以形成横向渐变的沟道区。

6. 发明授权

US06537860B2 Method of fabricating power VLSI diode devices 有权
公开(公告)号：US06537860B2
公开(公告)日：2003-03-25
申请号：US09739732
申请日：2000-12-18
申请人： Hidenori Akiyama , Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Haru Ohkawa , Yasuo Ohtsuki , Vladimir Rodov
发明人： Hidenori Akiyama , Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Haru Ohkawa , Yasuo Ohtsuki , Vladimir Rodov
IPC分类号： H01L21332
CPC分类号： H01L29/6609 , H01L29/0619 , H01L29/7391 , H01L29/861
摘要： A method for manufacturing a discrete power rectifier device having a VLSI multi-cell design employs a two spacer approach to defining a P/N junction profile having good breakdown voltage characteristics. The method provides highly repeatable device characteristics at reduced cost. The active channel regions of the device are also defined using the same two spacers. The method is a self-aligned process and channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations in spacer formation. Only two masking steps are required, and additional spacers for defining the body region profile can be avoided, reducing processing costs.

7. 发明授权

US06979861B2 Power device having reduced reverse bias leakage current 有权
标题翻译：功率器件具有降低的反向偏置漏电流
公开(公告)号：US06979861B2
公开(公告)日：2005-12-27
申请号：US10159558
申请日：2002-05-30
申请人： Vladimir Rodov , Paul Chang , Gary M. Hurtz , Geeng-Chuan Chern , Jianren Bao
发明人： Vladimir Rodov , Paul Chang , Gary M. Hurtz , Geeng-Chuan Chern , Jianren Bao
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L29/1095 , H01L29/66712 , H01L29/7802 , H01L29/861
摘要： A power device having vertical current flow through a semiconductor body of one conductivity type from a top electrode to a bottom electrode includes at least one gate electrode overlying a gate insulator on a first surface of the body, a channel region of second conductivity type in the surface of the body underlying all of the gate electrode, a first doped region of the second conductivity type contiguous with the channel region and positioned deeper in the body than the channel region and under a peripheral region of the gate electrode, and a second doped source/drain region in the surface of the body abutting the channel region and adjacent to the gate electrode. When the gate is forward biased, an inversion region extends through the channel region and electrically connects the first electrode and the second electrode with a small Vf near to the area between adjacent P bodies being flooded with electrons and denuded of holes. Therefore, at any forward bias this area conducts as an N-type region. When the gate electrode is reverse biased, the long channel region underlying the full length of the gate electrode reduces reverse leakage current.
摘要翻译：具有从顶部电极到底部电极的具有一种导电类型的半导体本体的垂直电流的功率器件包括在主体的第一表面上覆盖栅极绝缘体的至少一个栅极电极，第二导电类型的沟道区域所述第一导电类型的第一掺杂区域与所述沟道区域相邻并且位于所述体内比所述沟道区域更深的位置，并且位于所述栅电极的外围区域之下，以及第二掺杂源 /漏极区域，其邻接沟道区域并与栅电极相邻。当栅极被正向偏置时，反转区域延伸穿过沟道区域，并且在靠近被充满电子的相邻P体之间的区域附近以小的V sub电气连接第一电极和第二电极，裸露的洞因此，在任何正向偏置下，该区域作为N型区域进行。当栅电极被反向偏置时，栅电极全长下方的长沟道区域减少了反向泄漏电流。

8. 发明授权

US06426541B2 Schottky diode having increased forward current with improved reverse bias characteristics and method of fabrication 有权
公开(公告)号：US06426541B2
公开(公告)日：2002-07-30
申请号：US09729127
申请日：2000-12-01
申请人： Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Vladimir Rodov
发明人： Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Vladimir Rodov
IPC分类号： H01L27095
CPC分类号： H01L29/66143 , H01L21/2815 , H01L29/781 , H01L29/872
摘要： A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, a metal layer on the grooved surface and forming a Schottky junction with sidewalls of the grooved surface and ohmic contacts with top portions of the grooved surface. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body, and a plurality of doped regions at the bottom of grooves and forming P-N junctions with the semiconductor body. The P-N junctions of the doped regions form carrier depletion regions across and spaced from the grooves to increase the reverse bias breakdown voltage and reduce the reverse bias leakage current. The ohmic contacts of the metal layer increase forward current and reduce forward voltage of the Schottky diode.

9. 发明授权

US07964933B2 Integrated circuit including power diode 有权
标题翻译：集成电路包括功率二极管
公开(公告)号：US07964933B2
公开(公告)日：2011-06-21
申请号：US11821234
申请日：2007-06-22
申请人： Paul Chang , Geeng-Chuan Chern , Prognyan Ghosh , Wayne Y. W. Hsueh , Vladimir Rodov
发明人： Paul Chang , Geeng-Chuan Chern , Prognyan Ghosh , Wayne Y. W. Hsueh , Vladimir Rodov
IPC分类号： H01L21/76
CPC分类号： H01L27/0629 , H01L29/0692 , H01L29/78 , H01L29/861
摘要： A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.
摘要翻译：一种制造包括功率二极管的半导体集成电路的方法包括提供第一导电类型的半导体衬底，在衬底的第一区域中制造诸如CMOS晶体管电路的集成电路，并且在第二区域中制造功率二极管半导体衬底。介电材料形成在第一区域和第二区域之间，从而在第一区域中的集成电路与第二区域中的功率二极管之间提供电隔离。功率二极管可以包括由二极管的一个电极连接在一起的多个MOS源极/漏极元件和相关联的栅极元件，并且第二区域中的半导体层可以用作功率二极管的另一个源极/漏极。

10. 发明授权

US06399996B1 Schottky diode having increased active surface area and method of fabrication 有权
标题翻译：具有增加的活性表面积的肖特基二极管和制造方法
公开(公告)号：US06399996B1
公开(公告)日：2002-06-04
申请号：US09620074
申请日：2000-07-20
申请人： Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Vladimir Rodov
发明人： Paul Chang , Geeng-Chuan Chern , Wayne Y. W. Hsueh , Vladimir Rodov
IPC分类号： H01L77095
CPC分类号： H01L29/66143 , H01L21/2815 , H01L27/0727 , H01L27/0814 , H01L27/095 , H01L29/0634 , H01L29/781 , H01L29/872
摘要： A Schottky diode comprises a semiconductor body of one conductivity type, the semiconductor body having a grooved surface, and a metal layer on the grooved surface and forming a Schottky junction with the semiconductor body. The semiconductor body preferably includes a silicon substrate with the grooved surface being on a device region defined by a guard ring of a conductivity type opposite to the conductivity type of the semiconductor body.
摘要翻译：肖特基二极管包括一种导电类型的半导体本体，具有沟槽表面的半导体本体，以及在凹槽表面上形成与半导体本体的肖特基结的金属层。半导体本体优选地包括具有沟槽表面的硅衬底，该硅衬底在由与半导体本体的导电类型相反的导电类型的保护环限定的器件区域上。

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