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1. 发明授权

US06515330B1 Power device having vertical current path with enhanced pinch-off for current limiting 失效
标题翻译：具有垂直电流路径的功率器件，具有增强的夹断电流限制
公开(公告)号：US06515330B1
公开(公告)日：2003-02-04
申请号：US10037495
申请日：2002-01-02
申请人： Gary M. Hurtz , Vladimir Rodov , Geeng-Chuan Chern , Paul Chang , Ching-Lang Chiang
发明人： Gary M. Hurtz , Vladimir Rodov , Geeng-Chuan Chern , Paul Chang , Ching-Lang Chiang
IPC分类号： H01L2976
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/1095 , H01L29/66712 , H01L29/7802 , H01L29/861
摘要： A semiconductor current limiting device is provided by a two-terminal vertical N(P)-channel MOSFET device having the gate, body, and source terminals tied together as the anode and the drain terminal as the cathode. The doping profile of the body is so tailored with ion implantation that a depletion region pinches off to limit current. The body comprises a shallow implant to form a MOS channel and an additional deep implant through a spacer shielding the channel area. Implanted a higher energies and at an acute angle, the deep implant protrudes into the regular current path of the vertical MOSFET.
摘要翻译：半导体限流器件由两端垂直N（P）沟道MOSFET器件提供，其栅极，体和源极端子连接在一起作为阳极，漏极端子作为阴极。使用离子注入来定制主体的掺杂特性，耗尽区夹紧以限制电流。主体包括浅植入物以形成MOS通道，并通过隔离屏蔽通道区域的间隔物进行额外的深度注入。注入较高的能量并且以锐角，深的注入突出到垂直MOSFET的常规电流通路中。

2. 发明授权

US06979861B2 Power device having reduced reverse bias leakage current 有权
标题翻译：功率器件具有降低的反向偏置漏电流
公开(公告)号：US06979861B2
公开(公告)日：2005-12-27
申请号：US10159558
申请日：2002-05-30
申请人： Vladimir Rodov , Paul Chang , Gary M. Hurtz , Geeng-Chuan Chern , Jianren Bao
发明人： Vladimir Rodov , Paul Chang , Gary M. Hurtz , Geeng-Chuan Chern , Jianren Bao
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7811 , H01L29/1095 , H01L29/66712 , H01L29/7802 , H01L29/861
摘要： A power device having vertical current flow through a semiconductor body of one conductivity type from a top electrode to a bottom electrode includes at least one gate electrode overlying a gate insulator on a first surface of the body, a channel region of second conductivity type in the surface of the body underlying all of the gate electrode, a first doped region of the second conductivity type contiguous with the channel region and positioned deeper in the body than the channel region and under a peripheral region of the gate electrode, and a second doped source/drain region in the surface of the body abutting the channel region and adjacent to the gate electrode. When the gate is forward biased, an inversion region extends through the channel region and electrically connects the first electrode and the second electrode with a small Vf near to the area between adjacent P bodies being flooded with electrons and denuded of holes. Therefore, at any forward bias this area conducts as an N-type region. When the gate electrode is reverse biased, the long channel region underlying the full length of the gate electrode reduces reverse leakage current.
摘要翻译：具有从顶部电极到底部电极的具有一种导电类型的半导体本体的垂直电流的功率器件包括在主体的第一表面上覆盖栅极绝缘体的至少一个栅极电极，第二导电类型的沟道区域所述第一导电类型的第一掺杂区域与所述沟道区域相邻并且位于所述体内比所述沟道区域更深的位置，并且位于所述栅电极的外围区域之下，以及第二掺杂源 /漏极区域，其邻接沟道区域并与栅电极相邻。当栅极被正向偏置时，反转区域延伸穿过沟道区域，并且在靠近被充满电子的相邻P体之间的区域附近以小的V sub电气连接第一电极和第二电极，裸露的洞因此，在任何正向偏置下，该区域作为N型区域进行。当栅电极被反向偏置时，栅电极全长下方的长沟道区域减少了反向泄漏电流。

3. 发明授权

US08341582B2 Programmable analog tile configuration tool 有权
标题翻译：可编程模拟瓦片配置工具
公开(公告)号：US08341582B2
公开(公告)日：2012-12-25
申请号：US12322373
申请日：2009-01-30
申请人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
发明人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5063 , G06F2217/78
摘要： A programmable analog tile integrated circuit configuration tool communicates a power management control characteristic query soliciting control requirement information for a novel Power Management Integrated Circuit (PMIC) tile in a Multi-Tile Power Management Integrated Circuit (MTPMIC). The configuration tool receives a user response to the query indicating control requirements across a network. The PMIC tile includes configuration registers. Configuration information bit values stored in the configuration registers control the operational characteristics of the functional circuitry of the tile. The configuration registers of each novel PMIC tile are accessible at pre-defined addresses on a standardized bus of the MTPMIC. In response to the user response, the configuration tool generates appropriate tile configuration information for loading the configuration registers such that the PMIC tile within the MTPMIC is programmed to satisfy the user's control requirements.
摘要翻译：可编程模拟瓦片集成电路配置工具在多瓦片电源管理集成电路（MTPMIC）中传达用于新型电力管理集成电路（PMIC）瓦片的功率管理控制特性查询请求控制要求信息。配置工具通过网络收到用户对查询指示控制要求的响应。 PMIC瓦片包括配置寄存器。存储在配置寄存器中的配置信息位值控制瓦片的功能电路的操作特性。每个新型PMIC瓦片的配置寄存器可以在MTPMIC的标准化总线上的预定义地址处访问。响应于用户响应，配置工具生成用于加载配置寄存器的适当的瓦片配置信息，使得MTPMIC内的PMIC瓦片被编程以满足用户的控制要求。

4. 发明授权

US08225260B2 Programmable analog tile placement tool 有权
标题翻译：可编程模拟平铺放置工具
公开(公告)号：US08225260B2
公开(公告)日：2012-07-17
申请号：US12322376
申请日：2009-01-30
申请人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
发明人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.
摘要翻译：可编程模拟瓦片集成电路放置工具允许用户相对于所提出的多瓦功率管理集成电路（MTPMIC）中的第二PMIC瓦片的图形表示来操纵第一功率管理集成电路（PMIC）瓦片的图形表示）。新颖的PMIC瓦片具有预定义的物理结构，包括总线部分和用于存储用于配置瓦片的配置信息的存储器结构。当适当地放置在MTPMIC中时，所选择的瓦片的总线部分自动形成标准化总线，其适应功能性MTPMIC所需的所有信号通信。在模拟电路设计中具有最少训练的远程用户可以命令在所提出的MTPMIC布局中放置各个瓦片。当接收到指示对PMIC瓦片的放置的满意的用户响应时，该工具快速且自动地生成适于制造MTPMIC的物理布局数据。

5. 发明申请

US20100199250A1 Analog tile selection, placement, configuration and programming tool 有权
标题翻译：模拟瓦片选择，布局，配置和编程工具
公开(公告)号：US20100199250A1
公开(公告)日：2010-08-05
申请号：US12322400
申请日：2009-01-30
申请人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
发明人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An Analog Tile Selection, Placement, Configuration and Programming (ATSPCP) tool communicates a power management characteristic query over a network. The query is displayed to a user on a webpage. The query is a solicitation for desired characteristics of a Power Management Integrated Circuit (PMIC). After receiving user requirements in a response to the query, the tool selects a number of power management integrated circuit tiles having pre-defined physical structures. The pre-defined structure of each tile includes a bus portion and a memory structure for storing configuring information for the tile. When combined in a Multi-Tile Power Management Integrated Circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC that meets the user requirements. The ATSPCP tool combines the physical layout data of each selected PMIC tile to form composite physical layout data for the overall MTPMIC.
摘要翻译：模拟平铺选择，放置，配置和编程（ATSPCP）工具通过网络传达电源管理特性查询。该查询将显示给网页上的用户。该查询是对电力管理集成电路（PMIC）的所需特性的征集。在对查询的响应中接收到用户要求之后，该工具选择多个具有预定义物理结构的功率管理集成电路瓦片。每个瓦片的预定义结构包括总线部分和用于存储瓦片的配置信息的存储器结构。当组合在多平铺电源管理集成电路（MTPMIC）中时，所选择的电路板的总线部分自动形成标准化总线，以适应功能满足用户要求的MTPMIC所需的所有信号通信。 ATSPCP工具将每个选定的PMIC瓦片的物理布局数据组合，形成整个MTPMIC的复合物理布局数据。

6. 发明申请

US20090200982A1 USB port with smart power management 有权
标题翻译： USB端口，智能电源管理
公开(公告)号：US20090200982A1
公开(公告)日：2009-08-13
申请号：US12069955
申请日：2008-02-13
申请人： Gary M. Hurtz
发明人： Gary M. Hurtz
IPC分类号： H02J7/00 , H01M10/44
CPC分类号： H02J7/0054 , G06F1/3203 , G06F1/3253 , H01M10/44 , H02J2007/0062 , Y02D10/151 , Y10S323/901
摘要： A method involves detecting an inrush current that flows out of a USB port of a first electronic device when a central processing unit (CPU) of the first electronic device is not being powered. The inrush current is detected by a novel inrush current detect circuit when a second electronic device is connected to the USB port. In one example, the first electronic device is a laptop computer having a battery and a USB DC-to-DC converter. The inrush current detect circuit enables the USB DC-to-DC converter such that the USB DC-to-DC converter receives power from the battery and supplies a regulated voltage to the second electronic device through the USB port while the CPU remains unpowered (not drawing power from the battery).
摘要翻译：一种方法包括当第一电子设备的中央处理单元（CPU）未被供电时，检测从第一电子设备的USB端口流出的浪涌电流。当第二电子设备连接到USB端口时，浪涌电流由新颖的浪涌电流检测电路检测。在一个示例中，第一电子设备是具有电池和USB DC-DC转换器的膝上型计算机。浪涌电流检测电路使USB DC-DC转换器能够使USB DC-DC转换器从电池接收电力，并通过USB端口将稳压电压提供给第二电子设备，同时CPU保持不动作从电池抽取电力）。

7. 发明授权

US08079007B2 Programmable analog tile programming tool 有权
标题翻译：可编程模拟瓦片编程工具
公开(公告)号：US08079007B2
公开(公告)日：2011-12-13
申请号：US12322374
申请日：2009-01-30
申请人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
发明人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F1/3203 , G06F2217/64 , G06F2217/78
摘要： A programmable analog tile integrated circuit programming tool communicates a power management control characteristic query soliciting control requirement information for a novel power management integrated circuit (PMIC) tile in a multi-tile power management integrated circuit (MTPMIC). The programming tool receives a user response to the query indicating control requirements across a network. The novel PMIC tiles have a pre-defined physical structure including all memory structures required for configuration of each tile and a bus portion. When combined in a multi-tile power management integrated circuit (MTPMIC), the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. The memory structure of each tile is individually addressable via the standardized bus. Thus, in response to control requirements, the programming tool programs a PMIC tile that is part of a MTPMIC to meet the control requirements.
摘要翻译：可编程模拟瓦片集成电路编程工具在多瓦片功率管理集成电路（MTPMIC）中传达新型功率管理集成电路（PMIC）瓦片的功率管理控制特性查询请求控制需求信息。编程工具通过网络接收用户对查询指示控制要求的响应。新颖的PMIC瓦片具有预定义的物理结构，包括用于配置每个瓦片和总线部分所需的所有存储器结构。当在多瓦片电源管理集成电路（MTPMIC）中组合时，所选择的瓦片的总线部分自动形成标准化总线，其适应功能性MTPMIC所需的所有信号通信。每个瓦片的存储器结构可以通过标准化总线单独寻址。因此，响应于控制要求，编程工具对作为MTPMIC一部分的PMIC瓦片进行编程，以满足控制要求。

8. 发明申请

US20090033363A1 Multi-function input terminal 有权
标题翻译：多功能输入端子
公开(公告)号：US20090033363A1
公开(公告)日：2009-02-05
申请号：US11888606
申请日：2007-08-01
申请人： Gary M. Hurtz , Richard L. Gray , David J. Kunst
发明人： Gary M. Hurtz , Richard L. Gray , David J. Kunst
IPC分类号： H03K19/0185
CPC分类号： H03K19/09429 , H03K19/1732
摘要： A single terminal is usable to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is tied low by an external connection, or 2) is tied high by an external connection, or 3) is floating or is substantially floating. If the circuit determines that the terminal is floating or is substantially floating, then the circuit sets an operational characteristic of a portion of the circuit (for example, sets a maximum current with which the circuit charges a battery) to have a value that is a function of a resistance of an external resistor coupled to the terminal. If no external resistor is present, then the terminal is floating and the operational characteristic is set to have a zero value. The terminal and circuit are particularly suited to use in a USB battery charger.
摘要翻译：单个端子可用于将集成电路配置为三种状态之一。集成电路内的电路耦合到终端，并确定终端：1）是否通过外部连接被连接为低电平，或者2）通过外部连接被连接到高电平，或3）浮动或基本上浮动。如果电路确定端子浮动或基本上是浮置的，则电路将电路的一部分的操作特性（例如，设置电路对电池充电的最大电流）设定为具有值耦合到端子的外部电阻器的电阻的功能。如果没有外部电阻器，则端子浮动，并且操作特性设置为零值。终端和电路特别适用于USB电池充电器。

9. 发明申请

US20100199249A1 Programmable analog tile placement tool 有权
标题翻译：可编程模拟平铺放置工具
公开(公告)号：US20100199249A1
公开(公告)日：2010-08-05
申请号：US12322376
申请日：2009-01-30
申请人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
发明人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A programmable analog tile integrated circuit placement tool allows a user to manipulate a graphical representation of a first power management integrated circuit (PMIC) tile with respect to a graphical representation of a second PMIC tile in a proposed Multi-Tile Power Management Integrated Circuit (MTPMIC). The novel PMIC tiles have pre-defined physical structures including a bus portion and a memory structure for storing configuration information for configuring the tile. When appropriately placed in a MTPMIC, the bus portions of the selected tiles automatically form a standardized bus that accommodates all signal communication required for a functioning MTPMIC. A remote user with minimal training in analog circuit design may command the placement of individual tiles in a proposed MTPMIC layout. Upon receiving a user response indicating satisfaction with the placement of PMIC tiles, the tool quickly and automatically generates physical layout data suitable for fabrication of the MTPMIC.
摘要翻译：可编程模拟瓦片集成电路放置工具允许用户相对于所提出的多瓦功率管理集成电路（MTPMIC）中的第二PMIC瓦片的图形表示来操纵第一功率管理集成电路（PMIC）瓦片的图形表示）。新颖的PMIC瓦片具有预定义的物理结构，包括总线部分和用于存储用于配置瓦片的配置信息的存储器结构。当适当地放置在MTPMIC中时，所选择的瓦片的总线部分自动形成标准化总线，其适应功能性MTPMIC所需的所有信号通信。在模拟电路设计中具有最少训练的远程用户可以命令在所提出的MTPMIC布局中放置各个瓦片。当接收到指示对PMIC瓦片的放置的满意的用户响应时，该工具快速且自动地生成适于制造MTPMIC的物理布局数据。

10. 发明申请

US20100199247A1 Communicating configuration information across a programmable analog tile to another tile 有权
标题翻译：将可编程模拟图块中的配置信息传递到另一个图块
公开(公告)号：US20100199247A1
公开(公告)日：2010-08-05
申请号：US12322375
申请日：2009-01-30
申请人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
发明人： Steven Huynh , Matthew A. Grant , Gary M. Hurtz , David J. Kunst , Trey A. Roessig
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F1/26 , G06F1/3203 , G06F12/1408 , G06F17/5063 , G06F2217/64 , G06F2217/78
摘要： A programmable analog tile integrated circuit is configured over a standardized bus by communicating tile configuration information from a first integrated circuit tile, through a second integrated circuit tile, to a third integrated circuit tile. Each of the three integrated circuit tiles is part of an integrated circuit. The standardized bus is formed when the tiles are placed adjacent one another. Data bus and control signal conductors of the adjacent tiles line up and interconnect such that each signal conductor is electrically connected to every tile. Tile configuration information may be written to a selected register identified by an address in any selected one of the tiles using the data bus and control lines, regardless of the relative physical locations of the tile sending and the tile receiving the information. Thus, tile configuration information may pass from one tile to another tile, through any number of intermediate tiles.
摘要翻译：通过将第一集成电路瓦片中的瓦片配置信息通过第二集成电路瓦片传送到第三集成电路瓦片，在标准化总线上配置可编程模拟瓦片集成电路。三个集成电路瓦片中的每一个是集成电路的一部分。当瓦片彼此相邻放置时，形成标准化总线。相邻瓦片的数据总线和控制信号导体排列并互连，使得每个信号导体电连接到每个瓦片。可以使用数据总线和控制线将瓦片配置信息写入由任何所选择的瓦片中的地址识别的所选择的寄存器，而不管瓦片发送和瓦片接收信息的相对物理位置。因此，瓦片配置信息可以通过任何数量的中间瓦片从一个瓦片传递到另一个瓦片。

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