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1. 发明申请

US20070235807A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR 有权
标题翻译：半导体器件结构及其方法
公开(公告)号：US20070235807A1
公开(公告)日：2007-10-11
申请号：US11742955
申请日：2007-05-01
申请人： Ted White , Alexander Barr , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean
发明人： Ted White , Alexander Barr , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean
IPC分类号： H01L29/786
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

2. 发明申请

US20060094169A1 Semiconductor device structure and method therefor 有权
标题翻译：半导体器件结构及其方法
公开(公告)号：US20060094169A1
公开(公告)日：2006-05-04
申请号：US10977423
申请日：2004-10-29
申请人： Ted White , Alexander Barr , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean
发明人： Ted White , Alexander Barr , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean
IPC分类号： H01L21/84 , H01L21/00
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/045 , H01L29/66772
摘要： Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
摘要翻译：在不同的晶体取向上制作了两种不同的晶体管类型，其中两者都形成在SOI上。衬底具有晶体取向之一的底层半导体层和另一晶体取向的上覆层。底层具有暴露在其上的部分外延生长保持下面的半导体层的晶体结构的氧掺杂半导体层。然后在氧掺杂半导体层上外延生长半导体层。在高温下的氧化步骤使得氧化物掺杂区域分离成氧化物和半导体区域。然后将氧化物区域用作SOI结构中的绝缘层，并且剩下的上覆半导体层具有与下面的半导体层相同的晶体取向。不同类型的晶体管形成在不同的结晶取向上。

3. 发明申请

US20050070056A1 SOI template layer 有权
标题翻译： SOI模板层
公开(公告)号：US20050070056A1
公开(公告)日：2005-03-31
申请号：US10670928
申请日：2003-09-25
申请人： Chun-Li Liu , Marius Orlowski , Matthew Stoker , Philip Tobin , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
发明人： Chun-Li Liu , Marius Orlowski , Matthew Stoker , Philip Tobin , Mariam Sadaka , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
IPC分类号： H01L20060101 , H01L21/00 , H01L21/338
CPC分类号： H01L29/161 , H01L21/26506 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/1054 , Y10S438/933
摘要： A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.
摘要翻译：用于在SOI衬底的模板层材料中注入空位的空位注入工艺。模板层材料具有在一些实施方案中包括锗和硅原子的晶体结构。然后在模板层材料上外延生长应变硅层，具有应力对电子和空穴迁移率的有益效果。进行空位注入处理以将空位和锗原子注入晶格结构中，其中锗原子与空位重新组合。一个实施方案中，进行氮化处理以在模板层材料上生长氮化物层，并以注入晶体结构中的空位并且还允许锗原子与空位复合的方式消耗硅。空位注入方法的其它实例包括硅化工艺，氧氮化工艺，含氯化物气体的氧化工艺或氧化工艺之后的惰性气体后烘烤工艺。

4. 发明申请

US20060084235A1 LOW RC PRODUCT TRANSISTORS IN SOI SEMICONDUCTOR PROCESS 有权
标题翻译： SOI半导体工艺中的低RC产品晶体管
公开(公告)号：US20060084235A1
公开(公告)日：2006-04-20
申请号：US10965964
申请日：2004-10-15
申请人： Alexander Barr , Olubunmi Adetutu , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean , Ted White
发明人： Alexander Barr , Olubunmi Adetutu , Bich-Yen Nguyen , Marius Orlowski , Mariam Sadaka , Voon-Yew Thean , Ted White
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/66636 , H01L29/78618
摘要： A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.
摘要翻译：半导体制造工艺包括在半导体衬底上的掩埋氧化物层（BOX）上形成半导体顶层的SOI晶片的晶体管栅极。设置在栅极两侧的源极/漏极沟槽被蚀刻到BOX层中。源极/漏极结构形成在沟槽内。源极/漏极结构的深度大于顶部硅层的厚度，并且源极/漏极结构的上表面大致与晶体管沟道重合，源极/漏极结构与栅极之间的垂直重叠可忽略不计。沟槽优选地延伸穿过BOX层以暴露硅衬底的一部分。源极/漏极结构优选外延地形成，并且可能包括富氧阶段和无氧阶段的两个阶段。两个外延级之间的热退火将在源极/漏极结构和衬底之间形成隔离电介质。

5. 发明申请

US20060228851A1 Method of making a dual strained channel semiconductor device 有权
标题翻译：制造双应变通道半导体器件的方法
公开(公告)号：US20060228851A1
公开(公告)日：2006-10-12
申请号：US11093801
申请日：2005-03-30
申请人： Mariam Sadaka , Alexander Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
发明人： Mariam Sadaka , Alexander Barr , Dejan Jovanovic , Bich-Yen Nguyen , Voon-Yew Thean , Shawn Thomas , Ted White
IPC分类号： H01L21/8238
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： According to the embodiments to the present disclosure, the process of making a dual strained channel semiconductor device includes integrating strained Si and compressed SiGe with trench isolation for achieving a simultaneous NMOS and PMOS performance enhancement. As described herein, the integration of NMOS and PMOS can be implemented in several ways to achieve NMOS and PMOS channels compatible with shallow trench isolation.
摘要翻译：根据本公开的实施例，制造双应变通道半导体器件的过程包括将应变Si和压缩SiGe与沟槽隔离相集成，以实现同时的NMOS和PMOS性能增强。如本文所述，NMOS和PMOS的集成可以以几种方式实现，以实现与浅沟槽隔离兼容的NMOS和PMOS沟道。

6. 发明申请

US20050181549A1 Semiconductor structure having strained semiconductor and method therefor 有权
标题翻译：具有应变半导体的半导体结构及其方法
公开(公告)号：US20050181549A1
公开(公告)日：2005-08-18
申请号：US10780143
申请日：2004-02-17
申请人： Alexander Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam Sadaka , Voon-Yew Thean , Ted White
发明人： Alexander Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam Sadaka , Voon-Yew Thean , Ted White
IPC分类号： H01L21/00 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/04
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/823412 , H01L21/823807 , H01L21/84
摘要： A first semiconductor structure has a silicon substrate, a first silicon germanium layer grown on the silicon, a second silicon germanium layer on the first silicon germanium layer, and a strained silicon layer on the second silicon germanium layer. A second semiconductor structure has a silicon substrate and an insulating top layer. The silicon layer of the first semiconductor structure is bonded to the insulator layer to form a third semiconductor structure. The second silicon germanium layer is cut to separate most of the first semiconductor structure from the third semiconductor structure. The silicon germanium layer is removed to expose the strained silicon layer where transistors are subsequently formed, which is then the only layer remaining from the first semiconductor structure. The transistors are oriented along the direction and at a 45 degree angle to the direction of the base silicon layer of the second silicon.
摘要翻译：第一半导体结构具有硅衬底，在硅上生长的第一硅锗层，第一硅锗层上的第二硅锗层和第二硅锗层上的应变硅层。第二半导体结构具有硅衬底和绝缘顶层。第一半导体结构的硅层被结合到绝缘体层以形成第三半导体结构。切割第二硅锗层以将大部分第一半导体结构与第三半导体结构分离。去除硅锗层以暴露随后形成晶体管的应变硅层，其后是从第一半导体结构残留的唯一层。晶体管沿着<100>方向定向并且与第二硅的基底硅层的<100>方向成45度角。

7. 发明申请

US20060068553A1 METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING A STRAINED CHANNEL AND A HETEROJUNCTION SOURCE/DRAIN 失效
标题翻译：形成具有应变通道和异常源/漏极的半导体器件的方法
公开(公告)号：US20060068553A1
公开(公告)日：2006-03-30
申请号：US10954121
申请日：2004-09-29
申请人： Voon-Yew Thean , Mariam Sadaka , Ted White , Alexander Barr , Venkat Kolagunta , Bich-Yen Nguyen , Victor Vartanian , Da Zhang
发明人： Voon-Yew Thean , Mariam Sadaka , Ted White , Alexander Barr , Venkat Kolagunta , Bich-Yen Nguyen , Victor Vartanian , Da Zhang
IPC分类号： H01L21/336
CPC分类号： H01L21/2254 , H01L29/665 , H01L29/66787 , H01L29/7848 , H01L29/785 , H01L29/78648
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

8. 发明申请

US20060084207A1 Channel orientation to enhance transistor performance 有权
标题翻译：通道方向增强晶体管性能
公开(公告)号：US20060084207A1
公开(公告)日：2006-04-20
申请号：US10969108
申请日：2004-10-20
申请人： Ted White , Alexander Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam Sadaka , Voon-Yew Thean
发明人： Ted White , Alexander Barr , Dejan Jovanovic , Bich-Yen Nguyen , Mariam Sadaka , Voon-Yew Thean
IPC分类号： H01L21/338
CPC分类号： H01L29/78 , H01L21/823807 , H01L27/092 , H01L29/045
摘要： P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide P channel transistor performance enhancement, the direction of their channel lengths is selected based on their channel direction. The narrow width P channel transistors are preferably oriented in the direction. The wide channel width P channel transistors are preferably oriented in the direction.
摘要翻译： P沟道晶体管形成在具有用于增强P沟道晶体管性能的（110）表面取向的半导体层中，并且N沟道晶体管形成在具有（100）表面取向的半导体层中。为了进一步提供P沟道晶体管性能增强，它们的沟道长度的方向根据其沟道方向来选择。窄宽度P沟道晶体管优选地在<100>方向上取向。宽通道宽度P沟道晶体管优选地在<110>方向上取向。

9. 发明申请

US20060065927A1 Double gate device having a heterojunction source/drain and strained channel 有权
标题翻译：具有异质结源/漏极和应变通道的双栅极器件
公开(公告)号：US20060065927A1
公开(公告)日：2006-03-30
申请号：US10952676
申请日：2004-09-29
申请人： Voon-Yew Thean , Mariam Sadaka , Ted White , Alexander Barr , Venkat Kolagunta , Bich-Yen Nguyen , Victor Vartanian , Da Zhang
发明人： Voon-Yew Thean , Mariam Sadaka , Ted White , Alexander Barr , Venkat Kolagunta , Bich-Yen Nguyen , Victor Vartanian , Da Zhang
IPC分类号： H01L29/06
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66628 , H01L29/66742 , H01L29/7842 , H01L29/78621 , H01L29/78648 , H01L29/78687
摘要： A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.
摘要翻译：半导体器件（10）通过将覆盖在优选硅的半导体层（16）上的栅极（22）定位而形成。例如仅SiGe或Ge的半导体材料（26）形成在半导体层上方的栅极和源极/漏极区域附近。热处理将应力源材料扩散到半导体层。发生横向扩散以形成应变通道（17），其中应力材料层（30）紧邻应变通道。延伸植入物从应力源材料层的第一部分产生源和漏植入物。应力源材料层的第二部分保留在应变通道和源极和漏极植入物之间的通道中。因此，在应变通道中形成异质结。在另一种形式中，发生应力源材料的氧化而不是延伸植入物以形成应变通道。

10. 发明申请

US20060040433A1 Graded semiconductor layer 有权
标题翻译：分级半导体层
公开(公告)号：US20060040433A1
公开(公告)日：2006-02-23
申请号：US10919952
申请日：2004-08-17
申请人： Mariam Sadaka , Shawn Thomas , Ted White , Chun-Li Liu , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean
发明人： Mariam Sadaka , Shawn Thomas , Ted White , Chun-Li Liu , Alexander Barr , Bich-Yen Nguyen , Voon-Yew Thean
IPC分类号： H01L21/84
CPC分类号： H01L29/78687 , H01L29/1054 , H01L29/6659 , H01L29/66742
摘要： A process for forming a semiconductor device. The process includes forming a template layer for forming a layer of strained silicon. In one example a layer of graded silicon germanium is formed where the germanium is at a higher concentration at the lower portion and at a lower concentration at a top portion. When subject to a condensation process, the germanium of the top portion of the layer diffuses to a remaining portion of the silicon germanium layer. Because the silicon germanium layer has a higher concentration of germanium at lower portions, germanium pile up after condensation may be reduced at the upper portion of the remaining portion of the silicon germanium layer.
摘要翻译：一种形成半导体器件的方法。该方法包括形成用于形成应变硅层的模板层。在一个示例中，形成梯度硅锗层，其中锗在下部处具有较高的浓度，在顶部处的浓度较低。当进行冷凝处理时，层的顶部的锗扩散到硅锗层的剩余部分。由于硅锗层在下部具有较高的锗浓度，所以在硅锗层的剩余部分的上部可以减少在冷凝后堆积的锗。

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