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1. 发明授权

US06263395B1 System and method for serial interrupt scanning 有权
标题翻译：串行中断扫描的系统和方法
公开(公告)号：US06263395B1
公开(公告)日：2001-07-17
申请号：US09227510
申请日：1999-01-06
申请人： Patrick L. Ferguson , Paul B. Rawlins , David F. Heinrich , Robert L. Woods
发明人： Patrick L. Ferguson , Paul B. Rawlins , David F. Heinrich , Robert L. Woods
IPC分类号： C06F1314
CPC分类号： G06F13/24
摘要： An interrupt controller may serially scan a plurality of interrupt request signals and/or receive interrupt request signals on parallel inputs. A scan latency may be associated with updating the status of serially scanned interrupt requests. Spurious interrupts may result from the scan latency. To reduce the chance of spurious interrupts, serially scanned interrupt requests may be masked for an amount of time following an end of interrupt (EOI). Write cycles to clear interrupt requests may be posted in a write buffer. The delay of such write cycles clearing the write buffer may also result in spurious interrupts. To reduce the chance of such spurious interrupts, EOI cycles may be delayed or retried until the write buffer empties.
摘要翻译：中断控制器可以串行地扫描多个中断请求信号和/或在并行输入上接收中断请求信号。扫描延迟可能与更新串行扫描中断请求的状态相关联。寄生中断可能是由扫描延迟引起的。为了减少伪中断的可能性，串行扫描的中断请求可能会在中断结束（EOI）之后被屏蔽一段时间。清除中断请求的写周期可能会发布在写缓冲区中。清除写缓冲区的这种写周期的延迟也可能导致虚假中断。为了减少这种虚假中断的机会，EOI周期可能被延迟或重试，直到写入缓冲器清空。

2. 发明授权

US06363439B1 System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system 有权
标题翻译：计算机系统中系统接口设备与总线接口设备之间的点对点串行通信的系统和方法
公开(公告)号：US06363439B1
公开(公告)日：2002-03-26
申请号：US09206515
申请日：1998-12-07
申请人： John D. Battles , Paul B. Rawlins , Robert Allan Lester , Patrick L. Ferguson
发明人： John D. Battles , Paul B. Rawlins , Robert Allan Lester , Patrick L. Ferguson
IPC分类号： G06F1314
CPC分类号： G06F13/4273 , G06F13/4004
摘要： A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units. A pull-up device may be provided on the serial communication link to maintain a high voltage level on the link when it is not being driven by one of the bus interface units. The north bridge and south bridge may alternate between sending and receiving commands across the
摘要翻译：提供系统接口单元和外围总线接口单元之间的点对点串行通信链路。系统总线接口单元可以在CPU总线和诸如PCI总线的外围总线之间进行接口，并且可以被称为北桥。系统接口单元也可以连接到主存储器和高级图形端口。外围总线接口单元可以在诸如PCI总线的第一外围总线和诸如ISA总线的第二外围总线之间进行接口，并且可以被称为南桥。系统接口单元和总线接口单元之间的串行通信链路可以是使用来自第一外设总线的总线时钟作为定时参考的单线串行总线。该时钟可能是PCI时钟。串行通信链路可以使用系统接口单元上的单个引脚和总线接口单元上的单个引脚在接口单元之间传输命令。可以在串行通信链路上提供上拉设备，以便当其不被总线接口单元中的一个驱动时，在链路上保持高电压电平。北桥和南桥可以在发送和接收命令之间交替

3. 发明授权

US07028213B2 Error indication in a raid memory system 有权
公开(公告)号：US07028213B2
公开(公告)日：2006-04-11
申请号：US09965883
申请日：2001-09-28
申请人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
发明人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
IPC分类号： G06F11/00
CPC分类号： G06F11/328 , G06F11/108 , G06F11/1092 , G06F2211/1052
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

4. 发明授权

US5590378A Apparatus for aligning and padding data on transfers between devices of different data widths and organizations 失效
标题翻译：用于对准和填充不同数据宽度和组织的设备之间传输的数据的装置
公开(公告)号：US5590378A
公开(公告)日：1996-12-31
申请号：US593176
申请日：1996-02-01
申请人： John S. Thayer , Patrick L. Ferguson
发明人： John S. Thayer , Patrick L. Ferguson
IPC分类号： G06F13/28 , G06F12/00 , G06F13/00
CPC分类号： G06F13/28
摘要： A computer system which includes a DMA controller on the local I/O unit which can be programmed by either the host processor or the local processor. Semaphore flags and lock bits are provided to allow determination of control of the local DMA controller and for passing information. Additionally, data alignment and padding circuitry is provided. The circuitry is informed of the logical data arrangement desired or utilized by the host processor or other devices and knows the data arrangement of the local processor. The circuitry properly obtains and realigns the data based on the transfer direction and data arrangement. The circuitry further properly zero pads the data when realignment is such that padding is necessary.
摘要翻译：一种计算机系统，其包括本地I / O单元上的DMA控制器，可由主机处理器或本地处理器进行编程。提供信号标志和锁定位以允许确定本地DMA控制器的控制和传递信息。另外，提供数据对准和填充电路。电路被通知主处理器或其他设备所期望或利用的逻辑数据布置，并且知道本地处理器的数据排列。电路根据传输方向和数据排列顺序获取和重新排列数据。当重新对准使得填充是必要的时，电路进一步适当地对数据进行填补。

5. 发明申请

US20120124397A1 POWER SWITCH CONTROL CIRCUITRY 有权
标题翻译：电源开关控制电路
公开(公告)号：US20120124397A1
公开(公告)日：2012-05-17
申请号：US13387633
申请日：2010-03-30
申请人： Robert C. Brooks , Patrick L. Ferguson
发明人： Robert C. Brooks , Patrick L. Ferguson
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/32
摘要： Electronic circuits and methods are provided for conserving power within computers and other apparatus. A logic circuit performs a logical operation on a plurality of variables thus deriving a corresponding output. The output is used to drive and maintain an open or closed state of an electronic switch, accordingly. The electronic switch is disposed between a source of electrical energy and a system power buss of a computer. The computer can assume very low power, full power and other respective operating modes in accordance with the present state of the electronic switch.
摘要翻译：提供电子电路和方法来节省计算机和其他设备中的功率。逻辑电路对多个变量执行逻辑运算，从而导出相应的输出。相应地，输出用于驱动和保持电子开关的打开或关闭状态。电子开关设置在电能源和计算机的系统功率总线之间。根据电子开关的当前状态，计算机可以承担非常低的功率，全功率和其他相应的工作模式。

6. 发明申请

US20140208140A1 POWER CONSUMPTION LIMIT ASSOCIATED WITH POWER OVER ETHERNET (POE) COMPUTING SYSTEM 有权
标题翻译：与以太网（POE）计算机系统的电源相关的功耗限制
公开(公告)号：US20140208140A1
公开(公告)日：2014-07-24
申请号：US14232918
申请日：2011-07-18
申请人： Robert C. Brooks , Jeffrey C. Stevens , Patrick L. Ferguson , Charles N. Shaver
发明人： Robert C. Brooks , Jeffrey C. Stevens , Patrick L. Ferguson , Charles N. Shaver
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/28 , G06F1/3209 , G06F1/3265 , G06F1/3296 , H04L12/10 , H04L12/40045 , Y02D10/153 , Y02D50/20
摘要： A computing system is associated with power consumption based on Power over Ethernet (PoE). Power consumption is compared to a threshold, and a signal is asserted that power consumption is to be limited based on the comparison to the threshold.
摘要翻译：计算系统与基于以太网供电（PoE）的功耗相关联。将功耗与阈值进行比较，并且根据与阈值的比较来确定功率消耗被限制的信号。

7. 发明授权

US07320086B2 Error indication in a raid memory system 失效
标题翻译：突袭存储系统中的错误指示
公开(公告)号：US07320086B2
公开(公告)日：2008-01-15
申请号：US11291243
申请日：2005-12-01
申请人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
发明人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
IPC分类号： G06F11/00
CPC分类号： G06F11/328 , G06F11/108 , G06F11/1092 , G06F2211/1052
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。系统实施错误中断控制，ECC错误报告，响应命令错误的墨盒错误关闭程序，每个DIMM的未使用的段中的错误信息的存储，热插拔过程指示器和存储卡和DIMM的远程标记功能。

8. 发明授权

US5596725A Fifo queue having replaceable entries 失效
标题翻译： Fifo队列具有可替换条目
公开(公告)号：US5596725A
公开(公告)日：1997-01-21
申请号：US196586
申请日：1994-02-14
申请人： Patrick L. Ferguson , David J. Maguire
发明人： Patrick L. Ferguson , David J. Maguire
IPC分类号： G06F5/10 , G06F7/00 , G06F13/00
CPC分类号： G06F5/10 , G06F7/00 , G06F2205/062
摘要： A FIFO queue is utilized to provide control information to the appropriate time slot in a time multiplexed serial link between an interface chip and a CODEC. The FIFO queue allows rewriting or replacement of any control registers present in the queue without requiring that a new entry be placed in the queue. A particular control register which is placed in the queue then maintains its place as the queue is emptied, even though the control register may be written one or more times while the control register entry is in the queue waiting for transmission to the CODEC. The loss of the prior command information is not a problem as the data rate of the serial link is still sufficiently high so that any minor transitory change which may have been desired would be of minimal effect in any regard and would have been inaudible to the human.
摘要翻译： FIFO队列用于在接口芯片和CODEC之间的时分复用串行链路中的适当时隙提供控制信息。 FIFO队列允许重写或替换队列中存在的任何控制寄存器，而不需要将新的条目放置在队列中。即使控制寄存器可能被写入一个或多次，而控制寄存器条目在等待传输到CODEC的队列中时，放置在队列中的特定控制寄存器随后保持其位置。丢失先前的命令信息不是问题，因为串行链路的数据速率仍然足够高，所以可能期望的任何轻微的暂时变化在任何方面都将是最小的影响，并且对于人类来说将是不可听见的。

9. 发明授权

US06981173B2 Redundant memory sequence and fault isolation 有权
标题翻译：冗余内存顺序和故障隔离
公开(公告)号：US06981173B2
公开(公告)日：2005-12-27
申请号：US09965877
申请日：2001-09-28
申请人： Patrick L. Ferguson , Robert A. Scheffler
发明人： Patrick L. Ferguson , Robert A. Scheffler
IPC分类号： H04L1/22 , G06F11/00
CPC分类号： H04L1/22
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion across on a plurality of memory cartridges each containing a plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). Each memory cartridge includes an independent memory controller and a corresponding control mechanism in the host/data controller to interpret the independent transitioning of each memory cartridge between various states, including a redundant-ready and a powerdown state to facilitate “hot-plug” capabilities utilizing the removable memory cartridges. Fault information may be passed between the individual memory controllers and the host/data controller to facilitate expedient fault isolation.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，该主机/数据控制器利用XOR引擎以跨条纹的方式在多个存储器盒上存储数据和奇偶校验信息，每个存储器盒包含多个存储器模块以创建工业标准DIMM（RAID）的冗余阵列。每个存储器盒包括独立的存储器控制器和主机/数据控制器中的对应的控制机制，以解释各种状态之间的每个存储器盒的独立转换，包括冗余就绪和掉电状态，以便于利用“热插拔”能力可移动存储盒。可以在各个存储器控制器和主机/数据控制器之间传递故障信息，以便于方便的故障隔离。

10. 发明授权

US06715116B2 Memory data verify operation 有权
标题翻译：内存数据验证操作
公开(公告)号：US06715116B2
公开(公告)日：2004-03-30
申请号：US09769958
申请日：2001-01-25
申请人： Robert A. Lester , John M. MacLaren , Patrick L. Ferguson , John E. Larson
发明人： Robert A. Lester , John M. MacLaren , Patrick L. Ferguson , John E. Larson
IPC分类号： G11C2900
CPC分类号： G06F11/1076 , G06F2211/1088 , G11C29/52
摘要： A system and technique for detecting data errors in a memory device. More specifically, data errors in a memory device are detected by initiating an internal READ command or verify operation from a set of logic which is internal to the memory system in which the memory devices reside. Rather than relying on a READ command to be issued from an external device, via a host controller, the verify logic initiates verify routine in response to an event such as an operator instruction, hot-plug operation, or a periodic schedule. By implementing the verify operation, the system does not rely on external READ commands to verify data integrity. The verify routine may rely on typical ECC error logging mechanisms and may be used in a RAID memory architecture. Further, the verify routine may be used in conjunction with other error logging and correction logic, as well as scrubbing logic.
摘要翻译：一种用于检测存储器件中的数据错误的系统和技术。更具体地，通过从存储器设备所在的存储器系统内部的一组逻辑启动内部READ命令或验证操作来检测存储器设备中的数据错误。验证逻辑不是依赖于通过主机控制器从外部设备发出READ命令，而是响应诸如操作员指令，热插拔操作或周期性调度的事件来启动验证程序。通过实施验证操作，系统不依赖外部READ命令来验证数据完整性。验证例程可能依赖于典型的ECC错误记录机制，并可用于RAID存储器架构。此外，验证程序可以与其他错误记录和校正逻辑以及擦洗逻辑结合使用。

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