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1. 发明授权

US06363439B1 System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system 有权
标题翻译：计算机系统中系统接口设备与总线接口设备之间的点对点串行通信的系统和方法
公开(公告)号：US06363439B1
公开(公告)日：2002-03-26
申请号：US09206515
申请日：1998-12-07
申请人： John D. Battles , Paul B. Rawlins , Robert Allan Lester , Patrick L. Ferguson
发明人： John D. Battles , Paul B. Rawlins , Robert Allan Lester , Patrick L. Ferguson
IPC分类号： G06F1314
CPC分类号： G06F13/4273 , G06F13/4004
摘要： A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provide. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units. A pull-up device may be provided on the serial communication link to maintain a high voltage level on the link when it is not being driven by one of the bus interface units. The north bridge and south bridge may alternate between sending and receiving commands across the
摘要翻译：提供系统接口单元和外围总线接口单元之间的点对点串行通信链路。系统总线接口单元可以在CPU总线和诸如PCI总线的外围总线之间进行接口，并且可以被称为北桥。系统接口单元也可以连接到主存储器和高级图形端口。外围总线接口单元可以在诸如PCI总线的第一外围总线和诸如ISA总线的第二外围总线之间进行接口，并且可以被称为南桥。系统接口单元和总线接口单元之间的串行通信链路可以是使用来自第一外设总线的总线时钟作为定时参考的单线串行总线。该时钟可能是PCI时钟。串行通信链路可以使用系统接口单元上的单个引脚和总线接口单元上的单个引脚在接口单元之间传输命令。可以在串行通信链路上提供上拉设备，以便当其不被总线接口单元中的一个驱动时，在链路上保持高电压电平。北桥和南桥可以在发送和接收命令之间交替

2. 发明授权

US5949436A Accelerated graphics port multiple entry gart cache allocation system and method 失效
标题翻译：加速图形端口多进入gart缓存分配系统和方法
公开(公告)号：US5949436A
公开(公告)日：1999-09-07
申请号：US941861
申请日：1997-09-30
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Jerome J. Johnson , Michael J. Collins
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Jerome J. Johnson , Michael J. Collins
IPC分类号： G06F12/10 , G06T1/60 , G06F15/00 , G06T1/00
CPC分类号： G06T1/60 , G06F12/1027 , G06F12/1081
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. When a GART table entry is not found in the cache, a memory access is required to obtained the needed GART table entry. There are two GART table entries in each quadword returned in toggle mode of the cacheline of memory information returned from the memory read access. At least one quadword (two GART table entries) are stored in the cache each time a memory access is required because of a cache miss.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）由核心逻辑芯片组使用，将AGP图形控制器使用的虚拟内存地址重新映射到驻留在计算机系统内存中的物理内存地址GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际使用不连续的块或物理系统存储器的页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针。核心逻辑芯片组可以缓存最近使用的GART表项的子集，以在执行地址转换时提高AGP性能。当缓存中没有找到GART表条目时，需要内存访问才能获取所需的GART表条目。在内存读取访问返回的内存信息的缓存行的切换模式下，每个四字中有两个GART表条目。由于缓存未命中，每次需要存储器访问时，至少有一个四字（两个GART表条目）存储在缓存中。

3. 发明授权

US08117420B2 Buffer management structure with selective flush 有权
标题翻译：具有选择性冲洗的缓冲区管理结构
公开(公告)号：US08117420B2
公开(公告)日：2012-02-14
申请号：US12187986
申请日：2008-08-07
申请人： Jian Shen , Robert Allan Lester
发明人： Jian Shen , Robert Allan Lester
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , Y02D10/13
摘要： A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.
摘要翻译：描述了用于处理系统的缓冲器管理结构。在一个实施例中，缓冲器管理结构包括存储模块和控制模块。存储模块包括读取位置，并且可以在写入条目中存储指示事务请求的有效状态的位。控制模块可以接收无效请求并修改该位以指示事务请求的无效状态，并且当事务请求处于读取位置时丢弃事务请求。

4. 发明授权

US07685411B2 Multi-mode instruction memory unit 有权
标题翻译：多模式指令存储单元
公开(公告)号：US07685411B2
公开(公告)日：2010-03-23
申请号：US11104115
申请日：2005-04-11
申请人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William C. Anderson , Robert Allan Lester , Phillip M. Jones
发明人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William C. Anderson , Robert Allan Lester , Phillip M. Jones
IPC分类号： G06F9/00
CPC分类号： G06F9/325 , G06F9/3802 , G06F9/3804 , G06F9/381
摘要： An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.
摘要翻译：指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从如果目标指令没有存储在第二存储器结构中的第一存储器结构。

5. 发明授权

US06470429B1 System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops 有权
标题翻译：用于将内存请求识别为非缓存或减少缓存一致性目录查找和总线侦听的系统
公开(公告)号：US06470429B1
公开(公告)日：2002-10-22
申请号：US09752128
申请日：2000-12-29
申请人： Phillip M. Jones , Robert Allan Lester
发明人： Phillip M. Jones , Robert Allan Lester
IPC分类号： G06F1200
CPC分类号： G06F12/0835 , G06F12/0831 , G06F12/0888
摘要： An apparatus for identifying requests to main memory as non-cacheable in a computer system with multiple processors includes a main memory, memory cache, processor and cache coherence directory all coupled to a host bridge unit (North bridge). The processor transmits requests for data to the main memory via the host bridge unit. The host bridge unit includes a cache coherence controller that implements a protocol to maintain the coherence of data stored in each of the processor caches in the computer system. A cache coherence directory is connected to the cache coherence controller. After receiving the request for data from main memory, the host bridge unit identifies requests for data to main memory as cacheable or non-cacheable. If the data is non-cacheable, then the host bridge unit does not request the cache coherence controller to perform a cache coherence directory lookup to maintain the coherence of the data.
摘要翻译：用于在具有多个处理器的计算机系统中将对主存储器的请求识别为不可缓存的装置包括全部耦合到主桥单元（北桥）的主存储器，存储器高速缓存，处理器和高速缓存一致性目录。处理器通过主机桥单元向主存储器发送数据请求。主机桥单元包括高速缓存一致性控制器，其执行协议以维持存储在计算机系统中的每个处理器高速缓存中的数据的一致性。高速缓存一致性目录连接到高速缓存一致性控制器。在从主存储器接收到数据请求之后，主桥单元将对主存储器的数据请求标识为可高速缓存或不可缓存。如果数据不可缓存，则主机桥单元不请求高速缓存一致性控制器执行高速缓存一致性目录查找以维持数据的一致性。

6. 发明申请

US20100037028A1 Buffer Management Structure with Selective Flush 有权
标题翻译：缓冲管理结构与选择性冲洗
公开(公告)号：US20100037028A1
公开(公告)日：2010-02-11
申请号：US12187986
申请日：2008-08-07
申请人： Jian Shen , Robert Allan Lester
发明人： Jian Shen , Robert Allan Lester
IPC分类号： G06F12/02
CPC分类号： G06F12/1027 , Y02D10/13
摘要： A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.
摘要翻译：描述了用于处理系统的缓冲器管理结构。在一个实施例中，缓冲器管理结构包括存储模块和控制模块。存储模块包括读取位置，并且可以在写入条目中存储指示事务请求的有效状态的位。控制模块可以接收无效请求并修改该位以指示事务请求的无效状态，并且当事务请求处于读取位置时丢弃事务请求。

7. 发明授权

US07155568B2 Transaction generator for initialization, rebuild, and verify of memory 有权
公开(公告)号：US07155568B2
公开(公告)日：2006-12-26
申请号：US09967610
申请日：2001-09-29
申请人： Elizabeth Anne Richard , John Edward Larson , Robert Allan Lester
发明人： Elizabeth Anne Richard , John Edward Larson , Robert Allan Lester
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F3/0601 , G06F11/108 , G06F11/1092 , G06F2003/0697 , G06F2211/1052
摘要： A transaction generator generates memory transactions identical to processor memory transactions to initialize, rebuild, and verify memory added or replaced during operation of a computer system configured for RAID memory. The transactions read and rewrite the correct value for replaced memory and write a known good value for added memory. Memory writes are verified by a read after the write transaction. The transaction generator is a state machine. A first counter is used for holding memory addresses of the transactions, automatically incrementing after each transaction. A second counter can throttle the generation of transactions by controlling the incrementation speed of the first counter. Transactions generated by the transaction generator have a transaction identifier, selected from a pool of available transaction identifiers. The transactions can complete out of order.

8. 发明授权

US06747563B2 Removable memory cartridge system for use with a server or other processor-based device 有权
标题翻译：可移动内存盒系统，用于与服务器或其他基于处理器的设备配合使用
公开(公告)号：US06747563B2
公开(公告)日：2004-06-08
申请号：US10437567
申请日：2003-05-14
申请人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
发明人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
IPC分类号： G08B2300
CPC分类号： G06F13/4081 , G06F13/409
摘要： A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.
摘要翻译：一种基于处理器的设备，其具有通过杠杆系统固定在底盘内的多个存储器盒。基于处理器的设备包括用于指示存储器系统操作条件的指示系统。当从基于处理器的设备移除存储器盒时，每个存储器盒具有保护组件以保护存储器盒内的存储器元件。基于处理器的设备是可操作的，使得可以从基于处理器的设备移除至少一个存储盒，而不影响基于处理器的设备的操作。

9. 发明授权

US5884095A Direct memory access controller having programmable timing 失效
标题翻译：具有可编程时序的直接存储器存取控制器
公开(公告)号：US5884095A
公开(公告)日：1999-03-16
申请号：US815731
申请日：1997-03-12
申请人： Jeff W. Wolford , Robert Allan Lester
发明人： Jeff W. Wolford , Robert Allan Lester
IPC分类号： G06F13/28 , G06F13/30 , G06F13/362
CPC分类号： G06F13/30 , G06F13/28 , G06F13/287 , G06F13/3625
摘要： An improved DMA controller having programmable data transfer timings. Not only is the total cycle time programmable, but the active and inactive period of the cycle are also programmable. An active timing register and an inactive timing register are used in conjunction with a countdown timer to determine the active and inactive periods of the data transfer cycle. The active time period is loaded into the timer during the active phase, with the end of the active phase being indicated by the timer timing out. Next, the inactive time period is loaded into the timer, which similarly times out to indicate the end of the inactive phase of the data transfer cycle.
摘要翻译：改进的DMA控制器，具有可编程数据传输定时。总循环时间不仅可编程，而且循环的有效和无效周期也可编程。一个有效的定时寄存器和一个无效的定时寄存器与倒计时定时器结合使用，以确定数据传输周期的有效和无效周期。有效时间段在有效阶段加载到定时器中，活动阶段的结束由定时器超时指示。接下来，将非活动时间段加载到定时器中，其类似地超时以指示数据传送周期的非活动阶段的结束。

10. 发明授权

US07116241B2 Removable memory cartridge system for use with a server or other processor-based device 有权
公开(公告)号：US07116241B2
公开(公告)日：2006-10-03
申请号：US10437571
申请日：2003-05-14
申请人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
发明人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
IPC分类号： G08B23/00
CPC分类号： G06F13/4081 , G06F13/409
摘要： A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

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