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1. 发明授权

US07320086B2 Error indication in a raid memory system 失效
标题翻译：突袭存储系统中的错误指示
公开(公告)号：US07320086B2
公开(公告)日：2008-01-15
申请号：US11291243
申请日：2005-12-01
申请人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
发明人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
IPC分类号： G06F11/00
CPC分类号： G06F11/328 , G06F11/108 , G06F11/1092 , G06F2211/1052
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。系统实施错误中断控制，ECC错误报告，响应命令错误的墨盒错误关闭程序，每个DIMM的未使用的段中的错误信息的存储，热插拔过程指示器和存储卡和DIMM的远程标记功能。

2. 发明授权

US07028213B2 Error indication in a raid memory system 有权
公开(公告)号：US07028213B2
公开(公告)日：2006-04-11
申请号：US09965883
申请日：2001-09-28
申请人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
发明人： Tim Majni , Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark , Patrick L. Ferguson , Siamak Tavallaei , Jeffrey S. Autor , Christian H. Post , Dan Fink , Jeffery Galloway , Bret D. Roscoe
IPC分类号： G06F11/00
CPC分类号： G06F11/328 , G06F11/108 , G06F11/1092 , G06F2211/1052
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. The system implements error interrupt control, ECC error reporting, cartridge error power down procedures in response to command errors, storage of error information in unused segments of each DIMM, hot-pug procedure indicator and remote tagging capabilities of memory cartridges and DIMMs.

3. 发明授权

US07010652B2 Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency 有权
标题翻译：支持非均匀内存多级条带化以最大化并发性的方法
公开(公告)号：US07010652B2
公开(公告)日：2006-03-07
申请号：US10928046
申请日：2004-08-27
申请人： Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark
发明人： Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark
IPC分类号： G06F12/00
CPC分类号： G11C29/846 , G11C5/04 , G11C29/74 , G11C29/886 , G11C2029/0409 , G11C2029/0411
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。

4. 发明授权

US06785785B2 Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency 有权
标题翻译：支持非均匀内存的多级剥离以最大化并发的方法
公开(公告)号：US06785785B2
公开(公告)日：2004-08-31
申请号：US09770759
申请日：2001-01-25
申请人： Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark
发明人： Gary J. Piccirillo , John M. MacLaren , Robert A. Lester , John E. Larson , Jerome J. Johnson , Benjamin H. Clark
IPC分类号： G06F1200
CPC分类号： G11C29/846 , G11C5/04 , G11C29/74 , G11C29/886 , G11C2029/0409 , G11C2029/0411
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。

5. 发明授权

US07194577B2 Memory latency and bandwidth optimizations 失效
标题翻译：内存延迟和带宽优化
公开(公告)号：US07194577B2
公开(公告)日：2007-03-20
申请号：US10652943
申请日：2003-08-29
申请人： Jerome J. Johnson , Benjamin H. Clark , Gary J. Piccirillo , John M. MacLaren
发明人： Jerome J. Johnson , Benjamin H. Clark , Gary J. Piccirillo , John M. MacLaren
IPC分类号： G06F12/00
CPC分类号： G06F13/1642
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。为了优化存储器带宽并减少内存延迟，在本RAID系统中实现了各种技术。现有技术包括提供双存储器仲裁器，通过芯片选择或库地址排序读取周期，提供可编程的上限和下限边界寄存器以便于可编程存储器映射，以及条带化和交织存储器数据以提供一个突发长度。

6. 发明授权

US06938133B2 Memory latency and bandwidth optimizations 失效
公开(公告)号：US06938133B2
公开(公告)日：2005-08-30
申请号：US09965913
申请日：2001-09-28
申请人： Jerome J. Johnson , Benjamin H. Clark , Gary J. Piccirillo , John M. MacLaren
发明人： Jerome J. Johnson , Benjamin H. Clark , Gary J. Piccirillo , John M. MacLaren
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/1642
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.

7. 发明授权

US06832286B2 Memory auto-precharge 有权
标题翻译：内存自动预充电
公开(公告)号：US06832286B2
公开(公告)日：2004-12-14
申请号：US10179081
申请日：2002-06-25
申请人： Jerome J. Johnson , Benjamin H. Clark , Gary J. Piccirillo , John M. MacLaren
发明人： Jerome J. Johnson , Benjamin H. Clark , Gary J. Piccirillo , John M. MacLaren
IPC分类号： G06F1200
CPC分类号： G06F13/4243
摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). To optimally run back to back cycles to the memory modules, a technique for providing de-rating parameters such that unnecessary latencies designed into the memory devices can be removed while the system is executing requests. By removing any unnecessary latency, cycle time and overall system performance can be improved.
摘要翻译：计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。为了最佳地运行到内存模块的反向循环，提供降级参数的技术，使得在系统执行请求时可以去除设计到存储器设备中的不必要的延迟。通过消除任何不必要的延迟，可以提高周期时间和整体系统性能。

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