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1. 发明授权

US06715011B1 PCI/PCI-X bus bridge with performance monitor 有权
公开(公告)号：US06715011B1
公开(公告)日：2004-03-30
申请号：US09583712
申请日：2000-05-31
申请人： Pat Allen Buckland , Daniel Marvin Neal , Steven Mark Thurber
发明人： Pat Allen Buckland , Daniel Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1300
CPC分类号： G06F11/349 , G06F11/3466 , G06F2201/86
摘要： A bus bridge for use in a data processing system is disclosed in which the bridge includes a primary bus interface coupled to a primary bus, a secondary bus interface coupled to a secondary bus, a performance monitor register; and a state machine connected to the primary and secondary bus interfaces and configured to record the occurrence of a specified event in the performance monitor register. In a host bridge embodiment of the bridge, the primary bus is a host bus of the data processing system and the secondary bus is a PCI bus or PCI-X bus. The bridge may monitor events such as accepting a posted memory write (PMW), accepting with split response a read request (RR), retrying a PMW, retrying a RR, disconnecting a PMW when the bridge is a target of the operation, and accepting a PMW, accepting a split read completion operation (SRC), accepting a RR with split response, accepting a split write request operation (SWR) with split response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, and disconnecting a SRC when the bridge is a master. In a PCI-X to PCI-X embodiment of the bridge, the bridge may monitor the primary, and secondary busses are PCI-X or PCI busses and the events monitored including accepting a PMW, accepting a SRC, accepting a RR with spilt response, accepting a SWR with split response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, disconnecting a PMW, and disconnecting a SRC when the bridge is a target and accepting a PMW, accepting a SRC, accepting a RR with split response, accepting a SWR with split response, accepting a RR with immediate response, accepting a SWR with immediate response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, disconnecting a PMW, and disconnecting a SRC when the bridge is a master. In either embodiment, the bridge may further include a mode register corresponding to each performance monitor register where the value of the mode register determines the specified activity monitored by the corresponding performance monitor register.

2. 发明授权

US06581129B1 Intelligent PCI/PCI-X host bridge 失效
标题翻译：智能PCI / PCI-X主机桥
公开(公告)号：US06581129B1
公开(公告)日：2003-06-17
申请号：US09414339
申请日：1999-10-07
申请人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
发明人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
IPC分类号： G06F1336
CPC分类号： G06F13/4027
摘要： A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.
摘要翻译：公开了PCI主机桥和相关联的使用方法。 PCI主机桥包括主机总线接口，I / O总线接口和PCI操作检测电路。主机总线接口适用于与数据处理系统的主机总线进行通信，I / O总线接口适用于与PCI-X模式下工作的主PCI总线进行通信。 PCI操作检测电路适于检测可能从耦合到辅助PCI总线的PCI模式适配器发出的主PCI总线的PCI-X操作。检测电路还适于响应于确定PCI-X操作可能源自于PCI而产生用于转发到主机总线的修改操作。模式适配器。

3. 发明授权

US08782024B2 Managing the sharing of logical resources among separate partitions of a logically partitioned computer system 失效
标题翻译：管理逻辑分区计算机系统的不同分区之间的逻辑资源共享
公开(公告)号：US08782024B2
公开(公告)日：2014-07-15
申请号：US10777724
申请日：2004-02-12
申请人： Richard Louis Arndt , Bruce G. Mealey , Steven Mark Thurber
发明人： Richard Louis Arndt , Bruce G. Mealey , Steven Mark Thurber
IPC分类号： G06F7/00
CPC分类号： G06F9/45533 , G06F9/45541 , G06F9/5077
摘要： A mechanism is provided for sharing resources among logical partitions in a logical partitioned data processing system and for managing the changes to resources in such a way that the sharing operating systems are able to handle the various transitions in a graceful manner. Four hypervisor functions plus a specific return code manage the granting of access of resources owned by one partition to another (client) partition, accepting of granted resources by client partitions, returning of granted resources by client partitions, and rescinding of access by the owning partition. These four hypervisor functions are invoked either explicitly by the owning and client partitions or automatically by the hypervisor in response to partition termination. The hypervisor functions provide the needed infrastructure to manage the sharing of logical resources among partitions.
摘要翻译：提供了一种用于在逻辑分区数据处理系统中的逻辑分区之间共享资源并且以这样的方式管理对资源的改变的机制，使得共享操作系统能够以优雅的方式处理各种转换。四个管理程序功能加上特定的返回代码管理一个分区所拥有的资源到另一个（客户端）分区的授权，客户端分区接受授予的资源，客户机分区返回授权资源，以及由所拥有的分区撤销访问。这四个虚拟机管理程序功能由拥有和客户机分区明确地调用，或者由管理程序自动地响应于分区终止而调用。管理程序功能提供所需的基础设施来管理分区之间逻辑资源的共享。

4. 发明授权

US08213294B2 Mechanism for detecting and clearing I/O fabric lockup conditions for error recovery 有权
标题翻译：用于检测和清除I / O结构锁定条件以进行错误恢复的机制
公开(公告)号：US08213294B2
公开(公告)日：2012-07-03
申请号：US11426592
申请日：2006-06-27
申请人： Richard Louis Arndt , Thomas Schlipf , Steven Mark Thurber
发明人： Richard Louis Arndt , Thomas Schlipf , Steven Mark Thurber
IPC分类号： G01R31/08
CPC分类号： H04L47/10 , H04L41/0659 , H04L47/11 , H04L47/30 , H04L47/32 , H04L47/39 , H04L49/90
摘要： A computer implemented method, apparatus and mechanism for recovery of an I/O fabric that has become terminally congested or deadlocked due to a failure which causes buffers/queues to fill and thereby causes the root complexes to lose access to their I/O subsystems. Upon detection of a terminally congested or deadlocked transmit queue, access to such queue by other root complexes is suspended while each item in the queue is examined and processed accordingly. Store requests and DMA read reply packets in the queue are discarded, and load requests in the queue are processed by returning a special completion package. Access to the queue by the root complexes is then resumed.
摘要翻译：用于恢复I / O结构的计算机实现的方法，装置和机制，其由于导致缓冲器/队列填充并由此导致根配置失去对其I / O子系统的访问的故障而变得终端拥塞或死锁。在检测到最终拥塞或死锁传输队列时，暂停其他根组合对这样的队列的访问，同时对队列中的每个项目进行相应的检查和处理。队列中存储请求和DMA读回应数据包将被丢弃，队列中的加载请求将通过返回特殊的完成包进行处理。然后恢复根组合对队列的访问。

5. 发明授权

US07734842B2 Computer-implemented method, apparatus, and computer program product for managing DMA write page faults using a pool of substitute pages 有权
标题翻译：计算机实现的方法，设备和计算机程序产品，用于使用替代页面池管理DMA写页错误
公开(公告)号：US07734842B2
公开(公告)日：2010-06-08
申请号：US11390790
申请日：2006-03-28
申请人： Richard Louis Arndt , Steven Mark Thurber
发明人： Richard Louis Arndt , Steven Mark Thurber
IPC分类号： G06F13/28 , G06F12/08
CPC分类号： G06F11/141 , G06F12/08 , G06F12/1081
摘要： A computer-implemented method, apparatus, and computer program product are disclosed for managing direct memory access (DMA) write page faults using a pool of substitute pages. A computer system platform resolves a DMA write page fault for a page that is dedicated to an Input/Output (I/O) adapter. The I/O adapter attempts to write DMA data to the page. A determination is made that the page is unavailable for writing. The DMA data is then written to data locations in a substitute page that was selected from the pool of substitute pages. A flag is then set in a flag location for each one of the data locations. The flag locations correspond to the data locations. When a flag is set, the flag indicates that DMA write data is present in the data location that corresponds to that flag's flag location.
摘要翻译：公开了一种计算机实现的方法，装置和计算机程序产品，用于使用替代页面池来管理直接存储器访问（DMA）写页错误。计算机系统平台解决专用于输入/输出（I / O）适配器的页面的DMA写入页错误。 I / O适配器尝试将DMA数据写入页面。确定页面无法写入。然后将DMA数据写入从替代页面池中选择的替代页面中的数据位置。然后将标志设置在每个数据位置的标志位置。标志位置对应于数据位置。当标志置位时，标志表示DMA数据存在于该标志位置对应的数据位置。

6. 发明授权

US07398427B2 Isolation of input/output adapter error domains 有权
标题翻译：输入/输出适配器错误域的隔离
公开(公告)号：US07398427B2
公开(公告)日：2008-07-08
申请号：US10887524
申请日：2004-07-08
申请人： Richard Louis Arndt , Patrick Allen Buckland , Gregory Michael Nordstrom , Steven Mark Thurber
发明人： Richard Louis Arndt , Patrick Allen Buckland , Gregory Michael Nordstrom , Steven Mark Thurber
IPC分类号： G06F11/00
CPC分类号： G06F11/2736
摘要： Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data processing system, thus permitting the use of low cost, industry standard switches and bridges external to the host bridge.
摘要翻译：用于在数据处理系统中隔离输入/输出适配器错误域的方法，装置和系统。在一个输入/输出适配器中发生的错误与数据处理系统的其他输入/输出适配器隔离，主机桥中的功能将输入/输出适配器连接到数据处理系统的系统总线，从而允许使用低成本，行业标准交换机和主桥外部的桥梁。

7. 发明申请

US20070297434A1 MECHANISM FOR DETECTING AND CLEARING I/O FABRIC LOCKUP CONDITIONS FOR ERROR RECOVERY 有权
标题翻译：用于检测和清除错误恢复的I / O织物锁定条件的机制
公开(公告)号：US20070297434A1
公开(公告)日：2007-12-27
申请号：US11426592
申请日：2006-06-27
申请人： Richard Louis Arndt , Thomas Schlipf , Steven Mark Thurber
发明人： Richard Louis Arndt , Thomas Schlipf , Steven Mark Thurber
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L41/0659 , H04L47/11 , H04L47/30 , H04L47/32 , H04L47/39 , H04L49/90
摘要： A computer implemented method, apparatus and mechanism for recovery of an I/O fabric that has become terminally congested or deadlocked due to a failure which causes buffers/queues to fill and thereby causes the root complexes to lose access to their I/O subsystems. Upon detection of a terminally congested or deadlocked transmit queue, access to such queue by other root complexes is suspended while each item in the queue is examined and processed accordingly. Store requests and DMA read reply packets in the queue are discarded, and load requests in the queue are processed by returning a special completion package. Access to the queue by the root complexes is then resumed.
摘要翻译：用于恢复I / O结构的计算机实现的方法，装置和机制，其由于导致缓冲器/队列填充并由此导致根配置失去对其I / O子系统的访问的故障而变得终端拥塞或死锁。在检测到最终拥塞或死锁传输队列时，暂停其他根组合对这样的队列的访问，同时对队列中的每个项目进行相应的检查和处理。队列中存储请求和DMA读回应数据包将被丢弃，队列中的加载请求将通过返回特殊的完成包进行处理。然后恢复根组合对队列的访问。

8. 发明授权

US06654818B1 DMA access authorization for 64-bit I/O adapters on PCI bus 失效
标题翻译： PCI总线上64位I / O适配器的DMA访问授权
公开(公告)号：US06654818B1
公开(公告)日：2003-11-25
申请号：US09599179
申请日：2000-06-22
申请人： Steven Mark Thurber
发明人： Steven Mark Thurber
IPC分类号： G06F300
CPC分类号： G06F13/28 , G06F13/404
摘要： A method, data processing system, and I/O subsystem suitable for authorizing DMA accesses requested by a 64-bit I/O adapter are disclosed. The system includes one or more processors that have access to a system memory. A host bridge is connected between the processor(s) and an I/O bus. A first I/O adapter, which generates 32-bit addresses, is coupled to the host bridge. A second I/O adapter coupled to the host bridge is enabled to generate an address with a width greater than 32-bits (such as a 64-bit address). The system may include a Translation Control Entry (TCE) table, that is configured with information needed to translate an address generated by the 32-bit adapter to a wider address (such as a 64-bit address). In addition, the TCE may determine whether DMA access to the translated address by the requesting adapter is authorized. The system further includes an Access Control Table (ACT). The ACT determines whether DMA access to the address generated by the 64-bit I/O adapter is authorized. The ACT may be formatted as a set of ACT entries where each ACT entry corresponds to a unique portion of the system's memory address space. In one embodiment, each ACT entry consists of a single bit that indicates access to a 256 MB or larger portion of the system memory address space. In one embodiment, the I/O bus is a PCI bus. The first and second I/O adapters may be connected to a secondary PCI bus that communicates with the primary PCI bus via a PCI-to-PCI bridge. In one embodiment, each 64-bit I/O adapter has its own ACT table and portions of the ACT table may reside in the PCI-to-PCI bridge.
摘要翻译：公开了一种适用于授权由64位I / O适配器请求的DMA访问的方法，数据处理系统和I / O子系统。该系统包括可访问系统存储器的一个或多个处理器。主机桥连接在处理器和I / O总线之间。产生32位地址的第一个I / O适配器耦合到主机桥。耦合到主机桥的第二个I / O适配器能够生成宽度大于32位（例如64位地址）的地址。该系统可以包括翻译控制条目（TCE）表，其配置有将由32位适配器生成的地址转换为更宽的地址（例如64位地址）所需的信息。此外，TCE可以确定是否授权请求适配器对DMA转换的地址进行DMA访问。该系统还包括访问控制表（ACT）。 ACT确定是否授权对64位I / O适配器生成的地址的DMA访问。 ACT可以被格式化为一组ACT条目，其中每个ACT条目对应于系统的存储器地址空间的唯一部分。在一个实施例中，每个ACT条目由指示访问系统存储器地址空间的256MB或更大部分的单个位组成。在一个实施例中，I / O总线是PCI总线。第一和第二I / O适配器可以连接到通过PCI至PCI桥与主PCI总线通信的辅助PCI总线。在一个实施例中，每个64位I / O适配器具有其自己的ACT表，并且ACT表的部分可以驻留在PCI至PCI桥中。

9. 发明授权

US06493779B1 Method and system for interrupt handling using device pipelined packet transfers 失效
标题翻译：使用设备流水线分组传输的中断处理方法和系统
公开(公告)号：US06493779B1
公开(公告)日：2002-12-10
申请号：US09224111
申请日：1998-12-21
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译：提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。

10. 发明授权

US06418497B1 Method and system for interrupt handling using system pipelined packet transfers 失效
标题翻译：使用系统流水线分组传输的中断处理方法和系统
公开(公告)号：US06418497B1
公开(公告)日：2002-07-09
申请号：US09224119
申请日：1998-12-21
申请人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Guy Lynn Guthrie , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F948
CPC分类号： G06F13/26
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译：提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。

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