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1. 发明授权

US06581129B1 Intelligent PCI/PCI-X host bridge 失效
标题翻译：智能PCI / PCI-X主机桥
公开(公告)号：US06581129B1
公开(公告)日：2003-06-17
申请号：US09414339
申请日：1999-10-07
申请人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
发明人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
IPC分类号： G06F1336
CPC分类号： G06F13/4027
摘要： A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.
摘要翻译：公开了PCI主机桥和相关联的使用方法。 PCI主机桥包括主机总线接口，I / O总线接口和PCI操作检测电路。主机总线接口适用于与数据处理系统的主机总线进行通信，I / O总线接口适用于与PCI-X模式下工作的主PCI总线进行通信。 PCI操作检测电路适于检测可能从耦合到辅助PCI总线的PCI模式适配器发出的主PCI总线的PCI-X操作。检测电路还适于响应于确定PCI-X操作可能源自于PCI而产生用于转发到主机总线的修改操作。模式适配器。

2. 发明授权

US06665753B1 Performance enhancement implementation through buffer management/bridge settings 有权
标题翻译：通过缓冲管理/桥设置实现性能提升
公开(公告)号：US06665753B1
公开(公告)日：2003-12-16
申请号：US09637317
申请日：2000-08-10
申请人： Pat Allen Buckland , Michael Anthony Perez , Kiet Anh Tran , Adalberto Guillermo Yanes
发明人： Pat Allen Buckland , Michael Anthony Perez , Kiet Anh Tran , Adalberto Guillermo Yanes
IPC分类号： G06F300
CPC分类号： G06F13/4059
摘要： A method, system, and apparatus for modifying bridges within a data processing system to provide improved performance is provided. In one embodiment, the data processing system determines the number of input/output adapters connected underneath each PCI host bridge. The data processing system also determines the type of each input/output adapter. The size and number of buffers within the PCI host bridge is then modified based on the number of adapters beneath it as well as the type of adapters beneath it to improve data throughput performance as well as prevent thrashing of data. The PCI host bridge is also modified to give load and store operations priority over DMA operations. Each PCI-to-PCI bridge is modified based on the type of adapter connected to it such that the PCI-to-PCI bridge prefetches only an amount of data consistent with the type of adapter such that excess data is not thrashed, thus requiring extensive repetitive use of the system buses to retrieve the same data more than once.
摘要翻译：提供了一种用于修改数据处理系统内的网桥以提供改进性能的方法，系统和装置。在一个实施例中，数据处理系统确定在每个PCI主机桥下面连接的输入/输出适配器的数量。数据处理系统还确定每个输入/输出适配器的类型。然后，PCI主机桥中的缓冲区的大小和数量将根据其下的适配器数量以及其下的适配器类型进行修改，以提高数据吞吐量性能，并防止数据崩溃。还修改了PCI主机桥，以使加载和存储操作优先于DMA操作。每个PCI到PCI桥接器根据连接到它的适配器的类型进行修改，以使PCI-PCI桥只预取与适配器类型一致的数据量，以使得多余的数据不会被捶打，因此需要大量的重复使用系统总线多次检索相同的数据。

3. 发明授权

US06715011B1 PCI/PCI-X bus bridge with performance monitor 有权
公开(公告)号：US06715011B1
公开(公告)日：2004-03-30
申请号：US09583712
申请日：2000-05-31
申请人： Pat Allen Buckland , Daniel Marvin Neal , Steven Mark Thurber
发明人： Pat Allen Buckland , Daniel Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1300
CPC分类号： G06F11/349 , G06F11/3466 , G06F2201/86
摘要： A bus bridge for use in a data processing system is disclosed in which the bridge includes a primary bus interface coupled to a primary bus, a secondary bus interface coupled to a secondary bus, a performance monitor register; and a state machine connected to the primary and secondary bus interfaces and configured to record the occurrence of a specified event in the performance monitor register. In a host bridge embodiment of the bridge, the primary bus is a host bus of the data processing system and the secondary bus is a PCI bus or PCI-X bus. The bridge may monitor events such as accepting a posted memory write (PMW), accepting with split response a read request (RR), retrying a PMW, retrying a RR, disconnecting a PMW when the bridge is a target of the operation, and accepting a PMW, accepting a split read completion operation (SRC), accepting a RR with split response, accepting a split write request operation (SWR) with split response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, and disconnecting a SRC when the bridge is a master. In a PCI-X to PCI-X embodiment of the bridge, the bridge may monitor the primary, and secondary busses are PCI-X or PCI busses and the events monitored including accepting a PMW, accepting a SRC, accepting a RR with spilt response, accepting a SWR with split response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, disconnecting a PMW, and disconnecting a SRC when the bridge is a target and accepting a PMW, accepting a SRC, accepting a RR with split response, accepting a SWR with split response, accepting a RR with immediate response, accepting a SWR with immediate response, retrying a PMW, retrying a RR, retrying a SWR, retrying a SRC, disconnecting a PMW, and disconnecting a SRC when the bridge is a master. In either embodiment, the bridge may further include a mode register corresponding to each performance monitor register where the value of the mode register determines the specified activity monitored by the corresponding performance monitor register.

4. 发明授权

US06865615B1 Method and an apparatus for dynamically reconfiguring a system bus topology 失效
标题翻译：用于动态重新配置系统总线拓扑的方法和装置
公开(公告)号：US06865615B1
公开(公告)日：2005-03-08
申请号：US09620721
申请日：2000-07-20
申请人： Pat Allen Buckland , Scott Leonard Daniels , Thomas R. Forrer, Jr. , Daniel Eugene Pridgeon
发明人： Pat Allen Buckland , Scott Leonard Daniels , Thomas R. Forrer, Jr. , Daniel Eugene Pridgeon
IPC分类号： G06F13/40 , G06F15/16
CPC分类号： G06F13/4068
摘要： A method and an apparatus is presented for configuring a system bus topology dynamically. In a preferred embodiment, the system bus is a Small Computer System Interface (SCSI) bus that connects a “daisy” chain of disk drives. Two types of disk drives are used: single ended (SE) “Ultra” drives capable of 20 MHz operation and LVD (low voltage differential) “Ultra Plus” drives capable of 40 MHz operation. LVD disk drives can also function in the slower SE mode. The first drive in the chain of drives may need to be connected by a cable over three feet long. This introduces signal degradation that is often overcome by introducing redrive circuitry to boost signal quality. This is an expensive solution and a much easier solution is presented: install a jumper between the last drive in the chain and the first drive. However, if LVD bus mode is used, then this jumper solution does not work and the jumper must be removed. Disk drives in a server system are “hot swappable,” which means they can be changed at run time without shutting down the system. A method and an apparatus is provided for dynamically testing for the appropriate mode of bus operation based on the currently installed disk drives and adjusting the jumper setting accordingly.
摘要翻译：提出一种动态配置系统总线拓扑的方法和装置。在优选实施例中，系统总线是连接“菊花”链驱动器的小型计算机系统接口（SCSI）总线。使用两种类型的磁盘驱动器：具有20MHz操作的单端（SE）“Ultra”驱动器和能够进行40MHz操作的LVD（低电压差分）“Ultra Plus”驱动器。 LVD磁盘驱动器也可以在较慢的SE模式下运行。驱动器链中的第一个驱动器可能需要通过三英尺长的电缆连接。这导致信号劣化，通常通过引入重新启动电路来提升信号质量来克服。这是一个昂贵的解决方案，提供了一个更简单的解决方案：在链中的最后一个驱动器和第一个驱动器之间安装跳线。但是，如果使用LVD总线模式，则该跳线解决方案不起作用，并且必须移除跳线。服务器系统中的磁盘驱动器是“热插拔”，这意味着它们可以在运行时更改而不关闭系统。提供一种方法和装置，用于基于当前安装的磁盘驱动器动态测试适当的总线操作模式，并相应地调整跳线设置。

5. 发明授权

US06785783B2 NUMA system with redundant main memory architecture 失效
标题翻译： NUMA系统具有冗余主内存架构
公开(公告)号：US06785783B2
公开(公告)日：2004-08-31
申请号：US09726288
申请日：2000-11-30
申请人： Pat Allen Buckland
发明人： Pat Allen Buckland
IPC分类号： G06F1200
CPC分类号： G06F11/2071 , G06F11/1666 , G06F11/20 , G06F11/2058
摘要： A method and system for managing data in a data processing system are disclosed. Initially, data is stored in a first portion of the main memory of the system. Responsive to storing the data in the first portion of main memory, information is then stored in a second portion of the main memory. The information stored in the second portion of main memory is indicative of the data stored in the first portion. In an embodiment in which the data processing system is implemented as a multi-node system such as a NUMA system, the first portion of the main memory is in the main memory of a first node of system and the second portion of the main memory is in the main memory of a second node of the system. In one embodiment, storing information in the second portion of the main memory is achieved by storing a copy of the data in the second portion. If a fault in the first portion of the main memory is detected, the information in the second main memory portion is retrieved and stored to a persistent storage device. In another embodiment, storing information in the second portion of the main memory includes calculating a value based on the corresponding contents of other portions of the main memory using an algorithm such as checksum, parity, or ECC, and storing the calculated value in the second portion. In one embodiment, the main memory of at least one of the nodes is connectable to a persistent source of power, such as a battery, such that the main memory contents may be preserved if system power is disabled.
摘要翻译：公开了一种用于管理数据处理系统中的数据的方法和系统。最初，数据被存储在系统的主存储器的第一部分中。响应于将数据存储在主存储器的第一部分中，然后将信息存储在主存储器的第二部分中。存储在主存储器的第二部分中的信息指示存储在第一部分中的数据。在数据处理系统被实现为诸如NUMA系统的多节点系统的实施例中，主存储器的第一部分在系统的第一节点的主存储器中，并且主存储器的第二部分是在系统的第二个节点的主存储器中。在一个实施例中，通过在第二部分中存储数据的副本来将信息存储在主存储器的第二部分中。如果检测到主存储器的第一部分中的故障，则检索第二主存储器部分中的信息并将其存储到永久存储设备。在另一实施例中，在主存储器的第二部分中存储信息包括使用诸如校验和，奇偶校验或ECC的算法，基于主存储器的其他部分的相应内容计算值，并将计算的值存储在第二一部分。在一个实施例中，至少一个节点的主存储器可连接到诸如电池的持久电源，使得如果禁用系统电源，则可以保留主存储器内容。

6. 发明授权

US06467022B1 Extending adapter memory with solid state disks in JBOD and RAID environments 失效
标题翻译：在JBOD和RAID环境中扩展具有固态硬盘的适配器内存
公开(公告)号：US06467022B1
公开(公告)日：2002-10-15
申请号：US09706111
申请日：2000-11-03
申请人： Pat Allen Buckland , Ian David Judd , Gary Robert Lyons , Renato John Recio , Michael Francis Scully
发明人： Pat Allen Buckland , Ian David Judd , Gary Robert Lyons , Renato John Recio , Michael Francis Scully
IPC分类号： G06F1208
CPC分类号： G06F3/0656 , G06F3/0611 , G06F3/068 , G06F3/0689 , G06F11/1076 , G06F12/0866 , G06F2211/1009 , G06F2211/1054 , G06F2212/2022 , G06F2212/312
摘要： A Solid State Disk (“SSD”) and accompanying logic to extend the local memory of an adapter for RAID storage devices. Use of virtual memory, representing the SSD range of addresses in the adapter address memory, allows the adapter to incorporate the total memory into the adapter memory structure. The SSD is non-volatile and large amounts of cache items may be transferred to the SSD as an extension of the adapter memory. The cache write may be delayed and subsequently written to a designated address on a RAID drive, freeing the adapter on-board memory and control functions. Further, the size of the SSD allows for large amounts of data staging and storage, permitting device-to-device communications that would reduce the read and write commands between the host, adapter and drives.
摘要翻译：固态硬盘（“SSD”）以及用于扩展RAID存储设备适配器的本地内存的随附逻辑。使用虚拟内存，代表适配器地址存储器中的SSD范围的地址，允许适配器将总内存合并到适配器内存结构中。 SSD是非易失性的，并且大量的缓存项可以作为适配器存储器的扩展传送到SSD。高速缓存写入可能被延迟并随后写入RAID驱动器上的指定地址，释放适配器板上存储器和控制功能。此外，SSD的大小允许大量的数据分段和存储，允许设备到设备通信，这将减少主机，适配器和驱动器之间的读取和写入命令。

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