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1. 发明授权

US06581129B1 Intelligent PCI/PCI-X host bridge 失效
标题翻译：智能PCI / PCI-X主机桥
公开(公告)号：US06581129B1
公开(公告)日：2003-06-17
申请号：US09414339
申请日：1999-10-07
申请人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
发明人： Pat Allen Buckland , Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Scott Michael Willenborg , Curtis Carl Wollbrink , Adalberto Guillermo Yanes
IPC分类号： G06F1336
CPC分类号： G06F13/4027
摘要： A PCI host bridge and an associated method of use are disclosed. The PCI host bridge includes a host bus interface, an I/O bus interface, and a PCI operation detection circuit. The host bus interface is suitable for communicating with a host bus of a data processing system and the I/O bus interface is suitable for communicating with a primary PCI bus operating in PCI-X mode. The PCI operation detection circuit is adapted to detect a PCI-X operation from the primary PCI bus that may have issued from a PCI mode adapter coupled to a secondary PCI bus. The detection circuit is further adapted to generate a modified operation for forwarding to the host bus in response to determining that the PCI-X operation may have originated from a PCI. mode adapter.
摘要翻译：公开了PCI主机桥和相关联的使用方法。 PCI主机桥包括主机总线接口，I / O总线接口和PCI操作检测电路。主机总线接口适用于与数据处理系统的主机总线进行通信，I / O总线接口适用于与PCI-X模式下工作的主PCI总线进行通信。 PCI操作检测电路适于检测可能从耦合到辅助PCI总线的PCI模式适配器发出的主PCI总线的PCI-X操作。检测电路还适于响应于确定PCI-X操作可能源自于PCI而产生用于转发到主机总线的修改操作。模式适配器。

2. 发明授权

US06687240B1 Transaction routing system 失效
标题翻译：事务路由系统
公开(公告)号：US06687240B1
公开(公告)日：2004-02-03
申请号：US09377634
申请日：1999-08-19
申请人： Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
发明人： Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
IPC分类号： H04Q1100
CPC分类号： G06F13/4036
摘要： A method and implementing system is provided in which multiple nodes of a Peripheral Component Interconnect PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance. Transaction ordering rules are also implemented along with the arbiters to enable optimal information transfer management through the buffers, and routing tables are used to enable the addressing of all of the adapters on the plurality of PCI busses, and the efficient parallel peer-to-peer and Input/Output Processor IOP transfer of information between the adapter devices and also between the system and adapter devices on the PCI busses.
摘要翻译：提供了一种方法和实现系统，其中外围组件互连PCI桥接器/路由器电路的多个节点连接到对应的多个PCI总线，以使得能够在计算机系统内连接扩展数量的PCI适配器。实现多个增强型仲裁器以在仍然符合PCI系统要求的同时实现无阻塞和无死锁操作。示例性PCI到PCI路由器（PPR）电路包括仲裁器以及PPR缓冲器，用于临时存储通过PCI总线上的适配器之间和/或PCI适配器与CPU和系统存储器之间的路由器电路之间的交易相关信息或其他系统设备。实现缓冲区重命名方法以消除桥接缓冲器之间的内部请求/完成事务信息传输，从而提高系统性能。事务排序规则也与仲裁器一起实现，以通过缓冲器实现最佳信息传输管理，并且使用路由表来实现对多个PCI总线上的所有适配器的寻址，以及有效的并行对等以及输入/输出处理器IOP在适配器设备之间以及PCI总线上的系统和适配器设备之间的信息传输。

3. 发明授权

US06480923B1 Information routing for transfer buffers 有权
标题翻译：传输缓冲区的信息路由
公开(公告)号：US06480923B1
公开(公告)日：2002-11-12
申请号：US09377635
申请日：1999-08-19
申请人： Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
发明人： Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
IPC分类号： G06F1342
CPC分类号： G06F13/4036
摘要： A method and implementing system are provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance.
摘要翻译：提供了一种方法和实现系统，其中PCI桥/路由器电路的多个节点连接到相应的多个PCI总线，以使得能够在计算机系统内连接更多数量的PCI适配器。示例性PCI至PCI路由器（PPR）电路包括仲裁器以及PPR缓冲器，用于临时存储通过PCI总线上的适配器之间和/或PCI适配器与CPU和系统存储器之间的路由器电路的交易相关信息或其他系统设备。实现缓冲区重命名方法以消除桥接缓冲器之间的内部请求/完成事务信息传输，从而提高系统性能。

4. 发明授权

US06480917B1 Device arbitration including peer-to-peer access arbitration 失效
标题翻译：设备仲裁包括对等访问仲裁
公开(公告)号：US06480917B1
公开(公告)日：2002-11-12
申请号：US09377638
申请日：1999-08-19
申请人： Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
发明人： Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
IPC分类号： G06F1300
CPC分类号： G06F13/4036
摘要： A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance. Transaction ordering rules are also implemented along with the arbiters to enable optimal information transfer management through the buffers, and routing tables are used to enable the addressing of all of the adapters on the plurality of PCI busses, and the efficient parallel peer-to-peer and IOP transfer of information between the adapter devices and also between the system and adapter devices on the PCI busses.
摘要翻译：提供了一种方法和实现系统，其中PCI桥/路由器电路的多个节点连接到对应的多个PCI总线，以使得能够在计算机系统内连接扩展数量的PCI适配器。实现多个增强型仲裁器以在仍然符合PCI系统要求的同时实现无阻塞和无死锁操作。示例性PCI到PCI路由器（PPR）电路包括仲裁器以及PPR缓冲器，用于临时存储通过PCI总线上的适配器之间和/或PCI适配器与CPU和系统存储器之间的路由器电路之间的交易相关信息或其他系统设备。实现缓冲区重命名方法以消除桥接缓冲器之间的内部请求/完成事务信息传输，从而提高系统性能。事务排序规则也与仲裁器一起实现，以通过缓冲器实现最佳信息传输管理，并且使用路由表来实现对多个PCI总线上的所有适配器的寻址，以及有效的并行对等以及IOP在适配器设备之间以及PCI总线上的系统和适配器设备之间的信息传输。

5. 发明授权

US06418503B1 Buffer re-ordering system 有权
标题翻译：缓冲区重新排序系统
公开(公告)号：US06418503B1
公开(公告)日：2002-07-09
申请号：US09377633
申请日：1999-08-19
申请人： Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
发明人： Daniel Frank Moertl , Danny Marvin Neal , Steven Mark Thurber , Adalberto Guillermo Yanes
IPC分类号： G06F1310
CPC分类号： G06F13/4036
摘要： A method and implementing system is provided in which multiple nodes of a PCI bridge/router circuit are connected to corresponding plurality of PCI busses to enable an extended number of PCI adapters to be connected within a computer system. Multiple enhanced arbiters are implemented to enable non-blocking and deadlock-free operation while still complying with PCI system requirements. An exemplary PCI-to-PCI router (PPR) circuit includes the arbiters as well as PPR buffers for temporarily storing transaction-related information passing through the router circuit between adapters on the PCI busses and/or between PCI adapters and the CPUs and system memory or other system devices. A buffer re-naming methodology is implemented to eliminate internal request/completion transaction information transfers between bridge buffers thereby increasing system performance. Transaction ordering rules are also implemented along with the arbiters to enable optimal information transfer management through the buffers, and routing tables are used to enable the addressing of all of the adapters on the plurality of PCI busses, and the efficient parallel peer-to-peer and IOP transfer of information between the adapter devices and also between the system and adapter devices on the PCI busses.
摘要翻译：提供了一种方法和实现系统，其中PCI桥/路由器电路的多个节点连接到对应的多个PCI总线，以使得能够在计算机系统内连接扩展数量的PCI适配器。实现多个增强型仲裁器以在仍然符合PCI系统要求的同时实现无阻塞和无死锁操作。示例性PCI到PCI路由器（PPR）电路包括仲裁器以及PPR缓冲器，用于临时存储通过PCI总线上的适配器之间和/或PCI适配器与CPU和系统存储器之间的路由器电路之间的交易相关信息或其他系统设备。实现缓冲区重命名方法以消除桥接缓冲器之间的内部请求/完成事务信息传输，从而提高系统性能。事务排序规则也与仲裁器一起实现，以通过缓冲器实现最佳信息传输管理，并且使用路由表来实现对多个PCI总线上的所有适配器的寻址，以及有效的并行对等以及IOP在适配器设备之间以及PCI总线上的系统和适配器设备之间的信息传输。

6. 发明授权

US06957293B2 Split completion performance of PCI-X bridges based on data transfer amount 失效
标题翻译：基于数据传输量分割PCI-X网桥的完成性能
公开(公告)号：US06957293B2
公开(公告)日：2005-10-18
申请号：US10122989
申请日：2002-04-15
申请人： Daniel Frank Moertl , Adalberto Guillermo Yanes
发明人： Daniel Frank Moertl , Adalberto Guillermo Yanes
IPC分类号： G06F13/36 , G06F13/40
CPC分类号： G06F13/4027
摘要： Embodiments are provided in which a method is described for transferring data in a digital system including a first bus, a second bus, a PCI-X bridge coupling the first and second buses, and a first device and a second device residing on the first and second buses, respectively. The first bus has the same or higher bandwidth than that of the second bus. According to the method, the PCI-X bridge immediately starts or resumes forwarding split completion data from the first device to the second device if the first device starts or resumes split completion data transfer to the PCI-X bridge at the beginning of a block (i.e., the start or resume byte address has the form of 128N). If the first device starts transfer to the PCI-X bridge not at the beginning of a block, the PCI-X bridge refrains from forwarding split completion data until (a) the first device sends the data byte at the beginning of the next block to the PCI-X bridge or (b) the byte transfer count is exhausted, whichever occurs first.
摘要翻译：提供了一种描述用于在包括第一总线，第二总线，耦合第一和第二总线的PCI-X桥接器的数字系统中传送数据的方法以及驻留在第一总线上的第一设备和第二设备，第二辆巴士。第一条总线具有与第二条总线相同或更高的带宽。根据该方法，如果第一设备在块开始时启动或恢复到PCI-X桥接器的分离完成数据传输，则PCI-X桥立即启动或恢复从第一设备转发分组完成数据到第二设备（即，起始或恢复字节地址的形式为128N）。如果第一个设备开始传输到不在块开始处的PCI-X网桥，则PCI-X网桥不会转发分组完成数据，直到（a）第一个设备将下一个块开头的数据字节发送到 PCI-X网桥或（b）字节传输计数用尽，以先到者为准。

7. 发明授权

US06766405B2 Accelerated error detection in a bus bridge circuit 失效
标题翻译：总线桥式电路中的加速误差检测
公开(公告)号：US06766405B2
公开(公告)日：2004-07-20
申请号：US10109425
申请日：2002-03-28
申请人： Daniel Frank Moertl , Adalberto Guillermo Yanes
发明人： Daniel Frank Moertl , Adalberto Guillermo Yanes
IPC分类号： G06F1320
CPC分类号： G06F11/0751 , G06F11/0745 , G06F11/079 , G06F13/4059
摘要： A split operation such as a split read or a split write is handled by a bus bridge circuit. The bus bridge receives the read or write command from a requesting device, where the command includes a bus number for routing a completion of the command. The bus bridge then compares the bus number received from the requesting device with the return route bus number range of the bus bridge, and issues a split response to the requesting device if the bus number matches the return route bus number range of the bus bridge. If the bus number does not match the return route bus number range, then the command is aborted.
摘要翻译：诸如分离读取或分离写入的分离操作由总线桥接电路来处理。总线桥从请求设备接收读或写命令，其中命令包括用于路由命令完成的总线号。然后，总线桥将从请求设备接收的总线号与总线桥的返回路由总线编号范围进行比较，并且如果总线号与总线桥的返回路由总线数范围匹配，则向请求设备发出分离响应。如果总线编号与返回路由总线编号范围不匹配，则命令将中止。

8. 发明授权

US06519718B1 Method and apparatus implementing error injection for PCI bridges 失效
标题翻译：实现PCI桥接错误注入的方法和装置
公开(公告)号：US06519718B1
公开(公告)日：2003-02-11
申请号：US09506783
申请日：2000-02-18
申请人： Charles Scott Graham , Kevin Dale Jones , Daniel Frank Moertl , Adalberto Guillermo Yanes
发明人： Charles Scott Graham , Kevin Dale Jones , Daniel Frank Moertl , Adalberto Guillermo Yanes
IPC分类号： H04L124
CPC分类号： H04L1/24 , G06F11/221
摘要： A method and apparatus are provided for implementing error injection for peripheral component interconnect (PCI) bridges. The apparatus for implementing error injection for peripheral component interconnect (PCI) bridges includes a plurality of PCI busses and a control logic coupled to the plurality of PCI busses. The control logic targets a selected bus of the plurality of PCI busses. A hit is detected on the selected bus. Responsive to the detected hit, an error is injected on the selected bus. For a detected hit for predefined bug types, the operation must match a selected read or write, target or master, command type and the address must match unmasked address bits. For a detected hit for another predefined bug type, the PCI data bus must also match an unmask data register.
摘要翻译：提供了一种用于实现外围组件互连（PCI）桥的错误注入的方法和装置。用于实现外围组件互连（PCI）桥的错误注入的装置包括多个PCI总线和耦合到多个PCI总线的控制逻辑。控制逻辑针对多个PCI总线的选定总线。在所选择的总线上检测到命中。响应于检测到的命中，在所选择的总线上注入错误。对于检测到的预定义错误类型的命中，操作必须匹配所选的读取或写入，目标或主机命令类型，并且地址必须与未屏蔽的地址位匹配。对于另一预定义的错误类型的检测到的命中，PCI数据总线也必须与取消掩码数据寄存器匹配。

9. 发明授权

US06963990B2 Clock generation for multiple secondary buses of a PCI bridge 失效
标题翻译： PCI桥的多个二级总线的时钟生成
公开(公告)号：US06963990B2
公开(公告)日：2005-11-08
申请号：US10067785
申请日：2002-02-05
申请人： Jonathan Michael Allen , Steven Paul Jones , Daniel Frank Moertl , Adalberto Guillermo Yanes
发明人： Jonathan Michael Allen , Steven Paul Jones , Daniel Frank Moertl , Adalberto Guillermo Yanes
IPC分类号： G06F1/04 , G06F1/06 , G06F13/36 , G06F13/40
CPC分类号： G06F1/04 , G06F13/4027
摘要： Embodiments are provided in which clock generation for a PCI bridge and its N attached secondary buses is carried out by using an external PLL clock generator which generates N+1 first clock signals at a first frequency to the bridge and to N multiplexers. The bridge in turn generates N second clock signals to the N multiplexers. Each of the N clock signals generated by the bridge can be at either a second or third frequency. Each of the N multiplexers passes one of the first clock signal and second clock signal to a secondary bus depending on the speed of the slowest adapter on the secondary bus.
摘要翻译：提供了一种实施例，其中通过使用外部PLL时钟发生器来执行用于PCI桥及其N个附加辅助总线的时钟产生器，该外部PLL时钟发生器以第一频率向桥接器和N个多路复用器生成N + 1个第一时钟信号。该桥又产生N个第二时钟信号给N个多路复用器。由桥产生的N个时钟信号中的每一个可以是第二或第三频率。 N个多路复用器中的每一个根据辅助总线上最慢适配器的速度将第一时钟信号和第二时钟信号之一传递到辅助总线。

10. 发明授权

US06546447B1 Method and apparatus for dynamic PCI combining for PCI bridges 失效
标题翻译： PCI桥接动态PCI组合方法及装置
公开(公告)号：US06546447B1
公开(公告)日：2003-04-08
申请号：US09538212
申请日：2000-03-30
申请人： Patrick Allen Buckland , Daniel Frank Moertl , Adalberto Guillermo Yanes
发明人： Patrick Allen Buckland , Daniel Frank Moertl , Adalberto Guillermo Yanes
IPC分类号： G06F1336
CPC分类号： G06F13/4059
摘要： A method and apparatus are provided for implementing peripheral component interconnect (PCI) combining function for PCI bridges. A programmable boundary for a combined operation is selected. A write request is received. Responsive to the write request, checking for a combined operation hit is performed. Responsive to an identified combined operation hit, a combined operation is accepted. Checking for the selected programmable boundary for the combined operation is performed. Responsive to identifying the programmable boundary for the combined operation, the combined operation is launched to a destination bus. A programmable timer is identified for the combined operation. Responsive to the programmable timer expiring, the combined operation is launched to a destination bus. The programmable boundary for a combined operation is selected responsive to reading an adapter type and one of combining with a 128-byte boundary, combining with a 256-byte boundary, combining with a 512-byte boundary, or a posted memory write (PMW) is selected.
摘要翻译：提供了一种用于实现用于PCI桥的外围组件互连（PCI）组合功能的方法和装置。选择组合操作的可编程边界。接收到写请求。响应于写请求，执行检查组合操作命中。响应于确定的组合操作命中，组合操作被接受。执行组合操作的选择可编程边界的检查。响应于识别组合操作的可编程边界，将组合操作发送到目标总线。识别组合操作的可编程定时器。响应于可编程定时器到期，组合操作被发送到目标总线。组合操作的可编程边界是响应于读取适配器类型而选择的，并且与128字节边界组合，与256字节边界组合，与512字节边界组合或者已发布的存储器写入（PMW）被选中。

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