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1. 发明授权

US06823414B2 Interrupt disabling apparatus, system, and method 有权
标题翻译：中断禁用装置，系统和方法
公开(公告)号：US06823414B2
公开(公告)日：2004-11-23
申请号：US10087382
申请日：2002-03-01
申请人： Hiremane S. Radhakrishna
发明人： Hiremane S. Radhakrishna
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, optimize interrupt-handling by combining the activities of acknowledging and disabling the interrupt. In one embodiment, the apparatus may include an interrupt cause register coupled to an interrupt disabling register and an interrupt mask register. The system may include a processor coupled to an interrupt cause register using a bus, along with an interrupt disabling register coupled to an interrupt mask register and the interrupt disabling register. The method may include reading an interrupt cause register in response to receiving an interrupt, and transferring a mask value stored in an interrupt disabling register directly to an interrupt mask register so as to disable receiving further interrupts from the interrupt source.
摘要翻译：包括机器可访问介质的中断处理装置，系统和物品以及处理中断的方法通过组合确认和禁用中断的活动来优化中断处理。在一个实施例中，该装置可以包括耦合到中断禁用寄存器和中断屏蔽寄存器的中断引起寄存器。该系统可以包括使用总线耦合到中断引起寄存器的处理器，以及耦合到中断屏蔽寄存器和中断禁止寄存器的中断禁止寄存器。该方法可以包括响应于接收到中断而读取中断原因寄存器，并将存储在中断禁用寄存器中的掩码值直接传送到中断屏蔽寄存器，以便禁止从中断源接收进一步的中断。

2. 发明授权

US06775723B2 Efficient reading of a remote first in first out buffer 失效
公开(公告)号：US06775723B2
公开(公告)日：2004-08-10
申请号：US09961011
申请日：2001-09-21
申请人： Thomas A. Gregg , Stephen R. Burrow , Kulwant M. Pandey , Patrick J. Sugrue
发明人： Thomas A. Gregg , Stephen R. Burrow , Kulwant M. Pandey , Patrick J. Sugrue
IPC分类号： G06F1324
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0674 , G06F5/06
摘要： A method and system for a processor to efficiently accesses a remote First-in First-out (FIFO) buffer that is used to record event information. The access involves an interrupt mechanism when the FIFO transitions from the empty state, a mechanism for reading a FIFO entry including FIFO state information, and a mechanism for reading large areas of the FIFO while maintaining the pointers and interrupt protocols.

3. 发明授权

US06738847B1 Method for assigning a multiplicity of interrupt vectors in a symmetric multi-processor computing environment 有权
标题翻译：在对称多处理器计算环境中分配多个中断向量的方法
公开(公告)号：US06738847B1
公开(公告)日：2004-05-18
申请号：US09709075
申请日：2000-11-10
申请人： Andrew Ward Beale , Derek William Paul
发明人： Andrew Ward Beale , Derek William Paul
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A method is disclosed for use in a multi-processor computer system having a multiplicity of peripherals coupled thereto. The disclosed method assigns interrupt vectors from the multiplicity of peripherals, and includes the steps of determining if an interrupt resource from a given peripheral has already been assigned, and if not; assigning an affinity and vector to this interrupt resource. Moreover, a determination is made if the affinity and vector assigned in the previous step are within the operational characteristics of the multi-processor computer system.
摘要翻译：公开了一种用于具有与其耦合的多个外围设备的多处理器计算机系统中的方法。所公开的方法从多个外围设备分配中断向量，并且包括确定来自给定外设的中断资源是否已经被分配的步骤，如果不是; 为此中断资源分配关联和向量。此外，如果在前一步骤中分配的亲和力和向量在多处理器计算机系统的操作特性之内，则确定。

4. 发明授权

US06711644B1 Apparatus and method for communicating the completion of asynchronous input/output 失效
标题翻译：用于传达异步输入/输出完成的装置和方法
公开(公告)号：US06711644B1
公开(公告)日：2004-03-23
申请号：US09627226
申请日：2000-07-27
申请人： Mathew Accapadi , Kumar V. Nallapati , Mysore Sathyanaraya Srinivas , James William VanFleet , Nasr-Eddine Walehiane , Michael William Wortman
发明人： Mathew Accapadi , Kumar V. Nallapati , Mysore Sathyanaraya Srinivas , James William VanFleet , Nasr-Eddine Walehiane , Michael William Wortman
IPC分类号： G06F1324
CPC分类号： G06F13/12
摘要： An apparatus and method for communicating the completion of asynchronous I/O requests is provided. In particular, the apparatus and method make use of a new function call which is capable of waiting for a predetermined number of I/O requests to be completed prior to returning to the calling application. Control blocks for the I/O requests are updated after a predetermined number of I/O requests have been completed, i.e. in a process context rather than in an interrupt context as in the known systems. In this way, the overhead associated with known asynchronous I/O system calls is reduced.
摘要翻译：提供了用于传送异步I / O请求的完成的装置和方法。特别地，该装置和方法利用能够在返回到呼叫应用程序之前等待预定数量的I / O请求完成的新功能调用。 I / O请求的控制块在已经完成预定数量的I / O请求之后被更新，即在已知系统中，即在处理环境而不是中断上下文中。以这种方式，减少了与已知的异步I / O系统调用相关联的开销。

5. 发明授权

US06704823B1 Method and apparatus for dynamic allocation of interrupt lines through interrupt sharing 失效
标题翻译：通过中断共享动态分配中断线的方法和装置
公开(公告)号：US06704823B1
公开(公告)日：2004-03-09
申请号：US09620723
申请日：2000-07-20
申请人： Michael Anthony Perez , Louis Gabriel Rodriguez
发明人： Michael Anthony Perez , Louis Gabriel Rodriguez
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A method and an apparatus is present for dynamically allocating a set of output interrupt lines at a host adapter to a set of input interrupt lines for card slots controlled by the host adapter. If the number of input interrupt lines is greater than the number of output lines, then interrupt sharing is necessary. The number of input interrupt lines can be determined automatically by scanning all the card slots or can be determined by values stored in lookup tables. The algorithm to determine a logical mapping of the input interrupt lines to the output lines, in cases where interrupt sharing is required, can be based on a number of factors. A simple approach is to distribute the interrupts as equally as possible. Another algorithm may take into account the expected frequency of interrupts based on the device involved. Yet another approach may use a set of predetermined priorities. Since these algorithms are implemented in firmware or software, they can be changed to meet a particular set of needs. Once the mapping is determined, the input interrupt lines are electronically connecting to the output interrupt lines using “glue logic” associated with the host adapter. After this mapping is accomplished, an interrupt mapping table is built and sent to the operating system.
摘要翻译：存在用于在主机适配器处动态地分配一组输出中断线到由主机适配器控制的卡插槽的一组输入中断线的方法和装置。如果输入中断线数大于输出线数，则需要进行中断共享。可以通过扫描所有卡插槽来自动确定输入中断线的数量，也可以通过查找表中存储的值来确定。在需要中断共享的情况下，确定输入中断线到输出线的逻辑映射的算法可以基于多个因素。一个简单的方法是尽可能平均地分配中断。另一种算法可以考虑基于所涉及的设备的中断的期望频率。另一种方法可以使用一组预定的优先级。由于这些算法是在固件或软件中实现的，因此可以进行更改以满足特定的需求。确定映射后，输入中断线将使用与主机适配器相关联的“胶合逻辑”电子连接到输出中断线。完成此映射后，构建中断映射表并将其发送到操作系统。

6. 发明授权

US06691195B1 Compact diagnostic connector for a motherboard of data processing system 失效
标题翻译：用于数据处理系统主板的紧凑型诊断连接器
公开(公告)号：US06691195B1
公开(公告)日：2004-02-10
申请号：US09519340
申请日：2000-03-06
申请人： Maximino Aguilar , Sanjay Gupta , Roy Moonseuk Kim , Yuan-Chang Lo , James Michael Stafford
发明人： Maximino Aguilar , Sanjay Gupta , Roy Moonseuk Kim , Yuan-Chang Lo , James Michael Stafford
IPC分类号： G06F1324
CPC分类号： G06F11/2733
摘要： A compact connector for a data processing system motherboard facilitates the performance of diagnostics on data processing system components. The connector includes first, second, and third terminals in communication with respective first, second, and third lines in the motherboard for serial port interrupts, system data, and keyboard interrupts, respectively. In an illustrative embodiment, the first and second lines comprise lines of an Industry Standard Architecture (ISA) bus, and the compact connector also includes a fourth terminal in communication with a fourth line in the motherboard for real-time-clock interrupts. This embodiment allows the motherboard to receive real-time-clock interrupts via the connector, so that a startup program of the data processing system may boot to an operating system that requires a real-time-clock. That operating system may then be utilized to test the motherboard. In addition, this embodiment allows one or more input devices in communication with the connector to be utilized to interact with the motherboard.
摘要翻译：用于数据处理系统主板的紧凑型连接器有助于数据处理系统组件的诊断性能。连接器包括与主板中的相应的第一，第二和第三线分别与串行端口中断，系统数据和键盘中断相通信的第一，第二和第三终端。在说明性实施例中，第一和第二线包括工业标准架构（ISA）总线的线，并且紧凑连接器还包括与母板中的第四线通信的第四终端，用于实时时钟中断。该实施例允许主板经由连接器接收实时时钟中断，使得数据处理系统的启动程序可以引导到需要实时时钟的操作系统。然后可以使用该操作系统来测试主板。此外，该实施例允许与连接器通信的一个或多个输入设备用于与主板交互。

7. 发明授权

US06633941B2 Reduced networking interrupts 有权
标题翻译：减少网络中断
公开(公告)号：US06633941B2
公开(公告)日：2003-10-14
申请号：US10255525
申请日：2002-09-25
申请人： Randall D. Dunlap , Patrick L. Connor , John A. Ronciak , Greg D. Cummings , Gary G. Li
发明人： Randall D. Dunlap , Patrick L. Connor , John A. Ronciak , Greg D. Cummings , Gary G. Li
IPC分类号： G06F1324
CPC分类号： G06F13/385
摘要： An apparatus and method for reducing operating system interrupts by queuing incoming network traffic units received by a network interface, where said units are received without interrupting a host environment on receiving queued units. However, if a predetermined number of received units have a same origin, then the host environment is interrupted as subsequent network traffic units are received by the network interface, until a predetermined number of network traffic units are subsequently received from a different origin. Notwithstanding queuing incoming network traffic units, the host environment is interrupted on expiration of a timeout period, or if a predetermined number of units have been queued.
摘要翻译：一种用于通过对由网络接口接收的传入网络流量单元进行排队来减少操作系统中断的装置和方法，其中所述单元被接收而不会在接收排队的单元时中断主机环境。然而，如果预定数量的接收单元具有相同的起始点，则由于随后的网络业务单元被网络接口接收，所以主机环境被中断，直到随后从不同的来源接收到预定数量的网络业务单元。尽管对进入的网络流量单元排队，主机环境在超时时间到期时被中断，或者如果预定数量的单元已经排队。

8. 发明授权

US06622185B1 System and method for providing a real-time programmable interface to a general-purpose non-real-time computing system 失效
标题翻译：用于向通用非实时计算系统提供实时可编程接口的系统和方法
公开(公告)号：US06622185B1
公开(公告)日：2003-09-16
申请号：US09395647
申请日：1999-09-14
申请人： Peter J. Johnson , Eric Bendall
发明人： Peter J. Johnson , Eric Bendall
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A system and method providing read-time external signals to and from a gaming application executing within a platform independent programming environment on a computing system. The system has an input packet queue located within a block of system RAM, a main processing module, and an intelligent I/O interface module all coupled to the main system bus. The system generates an input signal data packet in response to a change in state of one or more external signals. The intelligent I/O interface module itself includes a control processor, an plurality of external signal interfaces, and a dual-port RAM. The control processor generates and stores the input signal data packet within the dual-port RAM before asserting an interrupt signal to the main processing module. Finally, the interrupt signal causes the main processing module to transfer the input signal data packet from the dual-port RAM to the input packet queue. The main processing system retrieves the input signal data packets from the input queue by continually polling the queue and processing the packets in the order received.
摘要翻译：一种向在计算系统的独立于平台的程序环境中执行的游戏应用提供读取外部信号的系统和方法。系统具有位于系统RAM的块内的输入分组队列，主处理模块和全部耦合到主系统总线的智能I / O接口模块。该系统响应于一个或多个外部信号的状态改变而产生输入信号数据包。智能I / O接口模块本身包括控制处理器，多个外部信号接口和双端口RAM。在向主处理模块发出中断信号之前，控制处理器产生并将输入信号数据包存储在双端口RAM内。最后，中断信号使主处理模块将输入信号数据包从双端口RAM传输到输入数据包队列。主处理系统通过连续轮询队列并按接收到的顺序处理数据包，从输入队列中检索输入信号数据包。

9. 发明授权

US06618779B1 Method and apparatus for chaining interrupt service routines 有权
标题翻译：用于链接中断服务程序的方法和装置
公开(公告)号：US06618779B1
公开(公告)日：2003-09-09
申请号：US09580116
申请日：2000-05-30
申请人： Robert A. Branch
发明人： Robert A. Branch
IPC分类号： G06F1324
CPC分类号： G06F9/4812 , G06F9/32
摘要： A method of chaining interrupt service routines comprises creating a chain handler module and replacing an instruction in an existing interrupt service routine with a branch directed to the chain handler module.
摘要翻译：链接中断服务例程的方法包括创建链接处理程序模块，并用指向链接处理程序模块的分支替换现有中断服务程序中的指令。

10. 发明授权

US06606677B1 High speed interrupt controller 失效
标题翻译：高速中断控制器
公开(公告)号：US06606677B1
公开(公告)日：2003-08-12
申请号：US09520876
申请日：2000-03-07
申请人： Bitwoded Okbay , Andrew Dale Walls , Michael Joseph Azevedo
发明人： Bitwoded Okbay , Andrew Dale Walls , Michael Joseph Azevedo
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A high speed interrupt controller and interrupt discrimination scheme for a data communication system is provided, usable in a subsystem of a data communication system. The controller and its scheme may be used for expanding the number of interrupts to be efficiently received and discriminated by a processor having a limited number of interrupt input lines. The present invention can be used for optimizing the management of data within a shared bus with multiple masters, wherein a shared bus is connected to a plurality of bus masters and corresponding slaves and located between an external bus connected to a system processor, and an internal bus connected to an internal processor. The architecture utilizes the high speed interrupt controller device having a circuitry which has a plurality of interrupt lines and may have one output line and a control code, located in the device interrupt handler. The circuitry consists of a status register where an appropriate bit is set when an interrupt is received from an external interrupt source device, and an interrupt mask register which enables and disables certain interrupts. The control code is used for monitoring and controlling the circuitry and servicing the interrupts received by the processor.
摘要翻译：提供了一种用于数据通信系统的高速中断控制器和中断识别方案，可用于数据通信系统的子系统。控制器及其方案可以用于扩展有效接收和鉴别具有有限数量的中断输入线的处理器的中断数量。本发明可用于优化具有多个主机的共享总线内的数据管理，其中共享总线连接到多个总线主机和对应的从机，并且位于连接到系统处理器的外部总线与内部总线连接到内部处理器。该架构利用具有多个中断线的电路的高速中断控制器装置，并且可以具有位于设备中断处理器中的一个输出线和控制代码。该电路由一个状态寄存器组成，当外部中断源设备接收到一个中断时，该位置位适当位，中断屏蔽寄存器使能和禁止某些中断。控制代码用于监控和控制电路并为处理器接收的中断服务。

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