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1. 发明授权

US08492883B2 Semiconductor package having a cavity structure 有权
标题翻译：具有空腔结构的半导体封装
公开(公告)号：US08492883B2
公开(公告)日：2013-07-23
申请号：US12192702
申请日：2008-08-15
申请人： Pao-Huei Chang Chien , Ping-Cheng Hu , Chien-Wen Chen , Hsu-Yang Lee
发明人： Pao-Huei Chang Chien , Ping-Cheng Hu , Chien-Wen Chen , Hsu-Yang Lee
IPC分类号： H01L23/495
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.
摘要翻译：描述半导体封装和相关方法。在一个实施例中，封装包括管芯焊盘，多个引线，芯片和封装体。所述管芯焊盘包括：（1）外围边缘区域，其限定具有包括中心部分的空腔底部的空腔; （2）上倾斜部分; 和（3）下倾斜部分。每个引线包括上倾斜部分和下倾斜部分。芯片设置在空腔底部的中心部分并且连接到引线。封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。

2. 发明授权

US08115285B2 Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof 有权
标题翻译：具有保护层以提高表面安装及其制造方法的高级四边形扁平无铅芯片封装
公开(公告)号：US08115285B2
公开(公告)日：2012-02-14
申请号：US12192805
申请日：2008-08-15
申请人： Chien-Wen Chen , Yi-Shao Lai , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Pao-Huei Chang Chien , Ping-Cheng Hu , Hsu-Yang Lee
发明人： Chien-Wen Chen , Yi-Shao Lai , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Pao-Huei Chang Chien , Ping-Cheng Hu , Hsu-Yang Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.
摘要翻译：描述半导体封装和相关方法。在一个实施例中，封装包括管芯焊盘，多个引线，芯片，封装体和保护层。管芯焊盘包括上倾斜部分，下倾斜部分和限定具有空腔底部的空腔的周边边缘区域。每个引线包括上倾斜部分和下倾斜部分。芯片设置在腔体底部并耦合到引线。封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。保护层基本上覆盖至少一个引线的下倾斜部分和下表面。

3. 发明申请

US20090230523A1 ADVANCED QUAD FLAT NO LEAD CHIP PACKAGE HAVING A CAVITY STRUCTURE AND MANUFACTURING METHODS THEREOF 有权
标题翻译：高级四角平面无铅芯片包装及其制造方法
公开(公告)号：US20090230523A1
公开(公告)日：2009-09-17
申请号：US12192702
申请日：2008-08-15
申请人： Pao-Huei Chang Chien , Ping-Cheng Hu , Chien-Wen Chen , Hsu-Yang Lee
发明人： Pao-Huei Chang Chien , Ping-Cheng Hu , Chien-Wen Chen , Hsu-Yang Lee
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.
摘要翻译：描述半导体封装和相关方法。在一个实施例中，封装包括管芯焊盘，多个引线，芯片和封装体。所述管芯焊盘包括：（1）外围边缘区域，其限定具有包括中心部分的空腔底部的空腔; （2）上倾斜部分; 和（3）下倾斜部分。每个引线包括上倾斜部分和下倾斜部分。芯片设置在空腔底部的中心部分并且连接到引线。封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。

4. 发明授权

US08120152B2 Advanced quad flat no lead chip package having marking and corner lead features and manufacturing methods thereof 有权
标题翻译：具有标记和拐角引线特征的高级四边形无铅芯片封装及其制造方法
公开(公告)号：US08120152B2
公开(公告)日：2012-02-21
申请号：US12192761
申请日：2008-08-15
申请人： Pao-Huei Chang Chien , Ping-Cheng Hu , Chien-Wen Chen
发明人： Pao-Huei Chang Chien , Ping-Cheng Hu , Chien-Wen Chen
IPC分类号： H01L23/495
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a first plurality of leads disposed in a lead placement area around the die pad, a second plurality of leads disposed in corner regions of the lead placement area, a semiconductor chip on the die pad and coupled to each lead, and a package body. Each lead includes an upper sloped portion and a lower sloped portion. An average of surface areas of lower surfaces of each of the second plurality of leads is at least twice as large as an average of surface areas of lower surfaces of each of the first plurality of leads. The package body substantially covers the upper sloped portions of the leads. The lower sloped portions of the leads at least partially extend outwardly from a lower surface of the package body.
摘要翻译：描述半导体封装和相关方法。在一个实施例中，封装包括管芯焊盘，设置在管芯焊盘周围的引线放置区域中的第一多个引线，设置在引线放置区域的拐角区域中的第二多个引线，管芯焊盘上的半导体芯片，连接到每个引线和一个封装体。每个引线包括上倾斜部分和下倾斜部分。第二多个引线中的每一个的下表面的平均面积至少是第一多个引线中的每一个的下表面的平均表面积的两倍。封装主体基本上覆盖引线的上倾斜部分。引线的下倾斜部分至少部分地从包装体的下表面向外延伸。

5. 发明申请

US20090230525A1 ADVANCED QUAD FLAT NO LEAD CHIP PACKAGE HAVING MARKING AND CORNER LEAD FEATURES AND MANUFACTURING METHODS THEREOF 有权
标题翻译：先进的四层平板不具有标记和拐角导线特征的铅芯片包装及其制造方法
公开(公告)号：US20090230525A1
公开(公告)日：2009-09-17
申请号：US12192761
申请日：2008-08-15
申请人： Pao-Huei Chang Chien , Ping-Cheng Hu , Chien-Wen Chen
发明人： Pao-Huei Chang Chien , Ping-Cheng Hu , Chien-Wen Chen
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a first plurality of leads disposed in a lead placement area around the die pad, a second plurality of leads disposed in corner regions of the lead placement area, a semiconductor chip on the die pad and coupled to each lead, and a package body. Each lead includes an upper sloped portion and a lower sloped portion. An average of surface areas of lower surfaces of each of the second plurality of leads is at least twice as large as an average of surface areas of lower surfaces of each of the first plurality of leads. The package body substantially covers the upper sloped portions of the leads. The lower sloped portions of the leads at least partially extend outwardly from a lower surface of the package body.
摘要翻译：描述半导体封装和相关方法。在一个实施例中，封装包括管芯焊盘，设置在管芯焊盘周围的引线放置区域中的第一多个引线，设置在引线放置区域的拐角区域中的第二多个引线，管芯焊盘上的半导体芯片，连接到每个引线和一个封装体。每个引线包括上倾斜部分和下倾斜部分。第二多个引线中的每一个的下表面的平均面积至少是第一多个引线中的每一个的下表面的平均表面积的两倍。封装主体基本上覆盖引线的上倾斜部分。引线的下倾斜部分至少部分地从包装体的下表面向外延伸。

6. 发明申请

US20090230524A1 SEMICONDUCTOR CHIP PACKAGE HAVING GROUND AND POWER REGIONS AND MANUFACTURING METHODS THEREOF 审中-公开
标题翻译：具有接地和电源区域的半导体芯片封装及其制造方法
公开(公告)号：US20090230524A1
公开(公告)日：2009-09-17
申请号：US12192742
申请日：2008-08-15
申请人： Pao-Huei Chang Chien , Ping-Cheng Hu , Chien-Wen Chen
发明人： Pao-Huei Chang Chien , Ping-Cheng Hu , Chien-Wen Chen
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and related methods are described. In one embodiment the semiconductor package includes a die pad, a plurality of leads, a semiconductor chip, and a package body. The die pad includes a first part that includes a lower surface and a first peripheral edge region comprising a ground region. The die pad further includes a second part that is spaced apart from the first part and that includes a lower surface and a second peripheral edge region comprising a power region. The plurality of leads is disposed around the die pad. The semiconductor chip is disposed on the die pad and is electrically coupled to the ground region, the power region, and the plurality of leads. The package body is formed over the semiconductor chip and the plurality of leads.
摘要翻译：描述半导体封装和相关方法。在一个实施例中，半导体封装包括管芯焊盘，多个引线，半导体芯片和封装体。管芯焊盘包括包括下表面的第一部分和包括接地区域的第一外围边缘区域。芯片焊盘还包括与第一部分间隔开并且包括下表面的第二部分和包括功率区域的第二外围边缘区域。多个引线设置在管芯焊盘周围。半导体芯片设置在芯片焊盘上并且电耦合到接地区域，功率区域和多个引线。封装体形成在半导体芯片和多个引线上。

7. 发明授权

US10085128B2 File download method for mobile device, server and mobile device thereof, and computer-readable medium 有权
公开(公告)号：US10085128B2
公开(公告)日：2018-09-25
申请号：US13087377
申请日：2011-04-15
申请人： Po-Yen Lee , Chien-Wen Chen , Pai-Chang Yeh , Li-Wen Lian
发明人： Po-Yen Lee , Chien-Wen Chen , Pai-Chang Yeh , Li-Wen Lian
IPC分类号： G06F15/16 , H04W4/18 , H04L29/08
CPC分类号： H04W4/18 , H04L67/1002
摘要： A file download method for a mobile device, a server and a mobile device thereof, and a computer-readable medium are provided. In the method, the server obtains file identification information according to an access operation of a terminal device on a service website. When the file identification information corresponds to a file of a first type, the server transmits the file of the first type to the mobile device directly. When the file identification corresponds to a file of a second type, the server transmits the file identification information to the mobile device, so that the mobile device downloads the file of the second type according to the file identification information.

8. 发明授权

US08904326B2 Semiconductor device design method, system and computer program product 有权
标题翻译：半导体器件设计方法，系统和计算机程序产品
公开(公告)号：US08904326B2
公开(公告)日：2014-12-02
申请号：US13539258
申请日：2012-06-29
申请人： Mu-Jen Huang , Chih Chi Hsiao , Wei-Ting Lin , Tsung-Hsin Yu , Chien-Wen Chen , Yung-Chow Peng
发明人： Mu-Jen Huang , Chih Chi Hsiao , Wei-Ting Lin , Tsung-Hsin Yu , Chien-Wen Chen , Yung-Chow Peng
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036 , G06F17/505 , G06F17/5072 , G06F17/5077 , G06F17/5081
摘要： In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.
摘要翻译：在由至少一个处理器执行的半导体器件设计方法中，所述至少一个处理器提取半导体器件的布局中的至少一个电气部件的位置数据。由至少一个处理器提取与所述至少一个电气部件相关联并且基于所述半导体器件的操作的模拟的电压数据。基于所提取的位置数据，所提取的电压数据由所述至少一个处理器并入所述布局中以生成所述半导体器件的修改的布局。

9. 发明授权

US08806414B2 Method and system for layout parasitic estimation 有权
标题翻译：布局寄生估计方法和系统
公开(公告)号：US08806414B2
公开(公告)日：2014-08-12
申请号：US13484480
申请日：2012-05-31
申请人： Mu-Jen Huang , Yu-Sian Jiang , Yi-Ting Lin , Hsien-Yu Tseng , Heng Kai Liu , Chien-Wen Chen , Chauchin Su
发明人： Mu-Jen Huang , Yu-Sian Jiang , Yi-Ting Lin , Hsien-Yu Tseng , Heng Kai Liu , Chien-Wen Chen , Chauchin Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/82
摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.
摘要翻译：一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。

10. 发明授权

US08775993B2 Integrated circuit design flow with layout-dependent effects 有权
标题翻译：集成电路设计流程与布局相关的效果
公开(公告)号：US08775993B2
公开(公告)日：2014-07-08
申请号：US13601773
申请日：2012-08-31
申请人： Mu-Jen Huang , Yu-Sian Jiang , Chien-Wen Chen
发明人： Mu-Jen Huang , Yu-Sian Jiang , Chien-Wen Chen
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5009 , G06F17/5081
摘要： A design system for designing an integrated circuit that includes a processor, a memory coupled to the processor, and instructions to generate and edit a schematic of the integrated circuit, generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit, extract the at least one recommended layout parameter during a layout stage of the integrated circuit, and calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter, and a user interface configured to display at least one of the circuit performance parameter and layout constraints of the integrated circuit device of the integrated circuit.
摘要翻译：一种用于设计包括处理器，耦合到处理器的存储器和用于生成和编辑集成电路的原理图的指令的集成电路的设计系统，生成集成电路内的集成电路器件的至少一个推荐布局参数，在所述集成电路的布局阶段期间提取所述至少一个推荐的布局参数，以及使用所述至少一个推荐布局参数来计算所述集成电路的电路性能参数;以及用户界面，被配置为显示所述电路性能中的至少一个集成电路集成电路器件的参数和布局约束。

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