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1. 发明授权

US08745552B2 EDA tool and method, and integrated circuit formed by the method 有权
标题翻译： EDA工具和方法，并通过该方法形成集成电路
公开(公告)号：US08745552B2
公开(公告)日：2014-06-03
申请号：US13484488
申请日：2012-05-31
申请人： Hsien-Yu Tseng , Shih-Kai Lin , Chin-Shen Lin , Yu-Sian Jiang , Heng-Kai Liu , Mu-Jen Huang , Chien-Wen Chen
发明人： Hsien-Yu Tseng , Shih-Kai Lin , Chin-Shen Lin , Yu-Sian Jiang , Heng-Kai Liu , Mu-Jen Huang , Chien-Wen Chen
IPC分类号： G06F17/50
CPC分类号： H01L23/528 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L21/76816 , H01L23/53228 , H01L27/0207
摘要： A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.
摘要翻译：一种方法包括：访问表示集成电路（IC）的层的布局的数据，所述集成电路的层包括多个多边形，所述多边形限定电路图案，以划分数个（N）个光掩模，用于多个图案化半导体衬底的单层; 其中N大于1。对于布局中的每个N个平行多边形组合，彼此比用用于单一光掩模进行图案化的最小间隔更靠近，至少N-1个针脚被插入到该组内的每个多边形中以将每个多边形分成至少N个部分，例如不同多边形的相邻部分被分配给彼此不同的光掩模。表示将每个组中的每个部分分配给相应光掩模的数据被存储在非瞬时的计算机可读存储介质中，该介质可访问以用于制造N个光掩模的过程。

2. 发明申请

US20130320555A1 EDA TOOL AND METHOD, AND INTEGRATED CIRCUIT FORMED BY THE METHOD 有权
标题翻译： EDA工具和方法，以及通过该方法形成的集成电路
公开(公告)号：US20130320555A1
公开(公告)日：2013-12-05
申请号：US13484488
申请日：2012-05-31
申请人： Hsien YU-TSENG , Shih-Kai LIN , Chin-Shen LIN , Yu-Sian JIANG , Heng-Kai LIU , Mu-Jen HUANG , Chien-Wen CHEN
发明人： Hsien YU-TSENG , Shih-Kai LIN , Chin-Shen LIN , Yu-Sian JIANG , Heng-Kai LIU , Mu-Jen HUANG , Chien-Wen CHEN
IPC分类号： H01L27/00 , G06F17/50
CPC分类号： H01L23/528 , G06F17/5068 , G06F17/5081 , G06F2217/12 , H01L21/76816 , H01L23/53228 , H01L27/0207
摘要： A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N−1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.
摘要翻译：一种方法包括：访问表示集成电路（IC）的层的布局的数据，所述集成电路的层包括多个多边形，所述多边形限定电路图案，以划分数个（N）个光掩模，用于多个图案化半导体衬底的单层; 其中N大于1。对于布局中的每个N个平行多边形组合，彼此比用用于单一光掩模进行图案化的最小间隔更靠近，在该组内的每个多边形中插入至少N-1个针脚，以将每个多边形分成至少N个部分，例如不同多边形的相邻部分被分配给彼此不同的光掩模。表示将每个组中的每个部分分配给相应光掩模的数据被存储在非瞬时的计算机可读存储介质中，该介质可访问以用于制造N个光掩模的过程。

3. 发明授权

US08806414B2 Method and system for layout parasitic estimation 有权
标题翻译：布局寄生估计方法和系统
公开(公告)号：US08806414B2
公开(公告)日：2014-08-12
申请号：US13484480
申请日：2012-05-31
申请人： Mu-Jen Huang , Yu-Sian Jiang , Yi-Ting Lin , Hsien-Yu Tseng , Heng Kai Liu , Chien-Wen Chen , Chauchin Su
发明人： Mu-Jen Huang , Yu-Sian Jiang , Yi-Ting Lin , Hsien-Yu Tseng , Heng Kai Liu , Chien-Wen Chen , Chauchin Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/82
摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.
摘要翻译：一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。

4. 发明申请

US20070019525A1 Optical disc drive and method of judging disc type thereof 审中-公开
标题翻译：光盘驱动器及其盘类型判断方法
公开(公告)号：US20070019525A1
公开(公告)日：2007-01-25
申请号：US11487337
申请日：2006-07-17
申请人： Hsien-Yu Tseng , Cheng-Chung Ho
发明人： Hsien-Yu Tseng , Cheng-Chung Ho
IPC分类号： G11B7/00
CPC分类号： G11B19/12 , G11B7/00736 , G11B2007/0006
摘要： A method of judging a type of a disc includes recording a first value of a SBAD signal generated by an optical pickup when a DVD laser beam is emitted to the disc, and judging whether the disc is DVD or CD according to the first value. If the disc is CD, the method further includes judging whether the disc has a read-only type or a non-read-only type according to the first value, recording a second value of the SBAD signal when a CD laser beam is emitted, calculating an absolute value of a difference between the first and second values, judging whether the disc is CD-R or CD-ROM according to the absolute value if the disc has the read-only type, and judging whether the disc is CD-RW or otherwise judging whether the disc is CD-R or CD-ROM according to the second value if the disc has the non-read-only type.
摘要翻译：一种判断光盘类型的方法包括：当将DVD激光束发射到光盘时，记录由光学拾取器产生的SBAD信号的第一值，并根据该第一值判断光盘是DVD还是CD。如果光盘是CD，则该方法还包括根据第一值判断光盘是只读类型还是非只读类型，当CD激光束发射时记录SBAD信号的第二值，计算第一和第二值之间的差的绝对值，如果盘具有只读类型，则根据绝对值判断光盘是CD-R还是CD-ROM，并且判断光盘是CD-RW 或者如果盘具有非只读类型，则根据第二值判断盘是CD-R还是CD-ROM。

5. 发明授权

US07218587B2 Method for determining writing power of data recording devices 失效
标题翻译：确定数据记录装置的写入功率的方法
公开(公告)号：US07218587B2
公开(公告)日：2007-05-15
申请号：US10427906
申请日：2003-05-02
申请人： Hsien-Yu Tseng , Shih-Chieh Lee , Ching-Hwa Liu
发明人： Hsien-Yu Tseng , Shih-Chieh Lee , Ching-Hwa Liu
IPC分类号： G11B7/00
CPC分类号： G11B7/126
摘要： A method for determining the writing power of data recording devices. First, the inner circle and outer circle of recording media are processed with optimum power calibration (OPC) to obtain an inner circle optimum writing power and an outer circle optimum writing power respectively. The writing power is determined according to the inner circle optimum writing power, outer circle optimum writing power, and/or the time of write speed is raised from the minimum write speed to the maximum write speed of the data recording device.
摘要翻译：一种用于确定数据记录装置的写入功率的方法。首先，以最佳功率校准（OPC）处理记录介质的内圈和外圆，分别获得内圆最佳写功率和外圆最佳写功率。根据内圆最佳写入功率，外圆最佳写入功率和/或写入速度的时间从数据记录装置的最小写入速度升高到最大写入速度来确定写入功率。

6. 发明授权

US06922382B2 Method for adjusting the write speed of data recording device and apparatus thereof 有权
标题翻译：用于调整数据记录装置的写入速度的方法及其装置
公开(公告)号：US06922382B2
公开(公告)日：2005-07-26
申请号：US10357426
申请日：2003-02-04
申请人： Hsien-Yu Tseng , Shih-Chieh Lee , Ching-Hwa Liu
发明人： Hsien-Yu Tseng , Shih-Chieh Lee , Ching-Hwa Liu
IPC分类号： G11B20/10 , G11B5/09
CPC分类号： G11B20/10527 , G11B2020/10703 , G11B2020/10814
摘要： A method for adjusting the write speed of a data recording device and apparatus thereof. First, the recording media is written to at a write speed, during which the number of buffer underrun events is counted. Then, the write speed is adjusted according to the number of buffer underrun events until writing is finished.
摘要翻译：一种用于调整数据记录装置的写入速度的方法及其装置。首先，以写入速度写入记录介质，在该速度下对缓冲器欠载事件的数量进行计数。然后，根据缓冲区欠载事件的数量调整写入速度，直到写入完成。

7. 发明申请

US20130326447A1 METHOD AND SYSTEM FOR LAYOUT PARASITIC ESTIMATION 有权
标题翻译：用于布局PARASITIC估计的方法和系统
公开(公告)号：US20130326447A1
公开(公告)日：2013-12-05
申请号：US13484480
申请日：2012-05-31
申请人： Mu-Jen HUANG , Yu-Sian JIANG , Yi-Ting LIN , Hsien-Yu TSENG , Heng Kai LIU , Chien-Wen CHEN , Chauchin SU
发明人： Mu-Jen HUANG , Yu-Sian JIANG , Yi-Ting LIN , Hsien-Yu TSENG , Heng Kai LIU , Chien-Wen CHEN , Chauchin SU
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/82
摘要： A system comprises an electronic design automation (EDA) tool, for generating a schematic design of an integrated circuit (IC), generating a layout from the schematic design, editing the layout, and verifying the schematic design and layout. At least one non-transitory, computer readable storage medium, is provided for storing data representing the schematic design and the layout, the layout having a network of routing paths connecting at least two active layer devices of the IC design. An RC tool is provided for computing estimated parasitic capacitances of the routing paths of the network before verifying the schematic design and layout, and for inserting a capacitor corresponding to the estimated parasitic capacitance into the data representing the schematic design of the IC. A first device level simulation tool for simulating performance of the network based on the at least two active layer devices and the estimated parasitic capacitances.
摘要翻译：一种系统包括电子设计自动化（EDA）工具，用于产生集成电路（IC）的示意性设计，从原理图设计生成布局，编辑布局以及验证原理图设计和布局。提供了至少一个非暂时的计算机可读存储介质，用于存储表示示意图设计和布局的数据，该布局具有连接IC设计的至少两个有源层设备的路由路径网络。提供了一种RC工具，用于在验证原理图设计和布局之前计算网络路由路径的估计寄生电容，并将与估计的寄生电容对应的电容插入到表示IC原理图设计的数据中。用于基于至少两个有源层器件和估计的寄生电容来模拟网络的性能的第一器件级仿真工具。

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