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    • 2. 发明申请
    • Method for joining wafers at a low temperature and low stress
    • 在低温低应力下接合晶片的方法
    • US20020048900A1
    • 2002-04-25
    • US09887667
    • 2001-05-23
    • Nova Crystals, Inc.
    • Yu-Hwa LoJizhi Zhang
    • H01L021/30H01L021/46
    • H01L21/2007H01L21/187
    • The method of the present invention is used to join two dissimilar materials together, and particularly to transfer a film to a substrate when the difference in thermal expansion coefficients between the film and the substrate is very big. A hydrophilic surface is created on one material and an atmosphere reactive metal element is deposited on the surface of another material. When the materials are tightly contacted, with the reactive element pressed against the hydrophilic surface, the reactive metal element reacts with the moisture from the hydrophilic surface at room temperature. Strong bonds form during the reaction joining the two materials together. Because the procedure takes place at room temperature, extremely low stress is built in. The film joining is successful even with a big thermal expansion coefficient difference between the materials, such as exist between GaAs and silicon and between silicon and sapphire. The joined materials can sustain typical post-joining device process such as OMCVD growth, wet and dry etching, thin film deposition, and thermal annealing.
    • 本发明的方法用于将两种不同材料连接在一起,特别是当膜和基板之间的热膨胀系数差异非常大时,将膜转移到基板。 在一种材料上产生亲水表面,并且气氛反应性金属元素沉积在另一种材料的表面上。 当材料紧密接触时,反应元件压在亲水表面上,反应性金属元素在室温下与亲水表面的水分反应。 在将两种材料连接在一起的反应过程中形成强键。 因为该程序在室温下进行,所以内置极低的应力。即使GaAs与硅之间以及硅与蓝宝石之间的材料之间存在较大的热膨胀系数差,膜接合也是成功的。 接合的材料可以维持典型的后连接器件工艺,例如OMCVD生长,湿法和干蚀刻,薄膜沉积和热退火。
    • 3. 发明申请
    • Method for fabricating light emitting diodes
    • 制造发光二极管的方法
    • US20020068373A1
    • 2002-06-06
    • US09728636
    • 2000-12-01
    • Nova Crystals, Inc.
    • Yu-Hwa LoZuhua ZhuTuoh-Bin Ng
    • H01L021/00
    • H01L33/007H01L33/0062
    • This invention describes a method for fabricating light-emitting diodes with an improved external quantum efficiency on a transparent substrate. The LED device structure is mounted face-down on and bonded to a handling wafer. The LED dies on the transparent substrate are separated by applying mutually aligned separation cuts from both sides of the transparent substrate and by then cutting through the handling wafer and the substrate wafer. This method allow the use of substrates that are difficult to thin and cleave. Contacts can be applied from one side of the devices only. The method is suitable for low cost high volume manufacturing.
    • 本发明描述了一种在透明衬底上制造具有改进的外部量子效率的发光二极管的方法。 LED装置结构面朝下地安装在并结合到处理晶片上。 通过从透明基板的两侧施加相互对准的分离切口,然后通过处理晶片和基板晶片切割,分离透明基板上的LED管芯。 该方法允许使用难以稀释和切割的基底。 联系人只能从设备的一侧应用。 该方法适用于低成本大批量生产。
    • 4. 发明申请
    • Hetero-interface avalance photodetector
    • 杂交界面光电探测器
    • US20020066938A1
    • 2002-06-06
    • US09971316
    • 2001-10-03
    • Nova Crystals, Inc.
    • Alexandre PauchardYu-Hwa Lo
    • H01L031/06
    • H01L31/1075H01L31/02327H01L31/03046Y02E10/544
    • An avalanche photodetector (APD) is made from composite semiconductor materials. The absorption region of the APD is formed in a n-type InGaAs layer. The multiplication region of the APD is formed in a p-type silicon layer. The two layers are bonded together. The p-type silicon layer may be supported on an nnull type silicon substrate. A p-n junction formed at the interface between the silicon layer and the substrate. Alternatively, the n-type InGaAs layer may be supported on an InP substrate. In this case, a p-n junction is formed by making n-doped surface regions in the p-type silicon superlayer. In either case, the p-n junction is reverse biased for avalanche multiplication of charge carriers. The maximum of the electric field distribution in the APD under reverse bias operating conditions is located at p-n junction. This maximum is at a distance equal to about the thickness of the p-type silicon layer away from the absorption region. The electric field values in the absorption region depend primarily on the thickness and doping level of the p-type silicon layer. The electric field values in the absorption region are controllably set for obtaining high carrier velocities in the absorption region without causing carrier tunneling.
    • 雪崩光电探测器(APD)由复合半导体材料制成。 APD的吸收区域形成在n型InGaAs层中。 APD的乘法区域形成在p型硅层中。 两层结合在一起。 p型硅层可以被支撑在n +型硅衬底上。 在硅层和衬底之间的界面处形成的p-n结。 或者,n型InGaAs层可以被负载在InP衬底上。 在这种情况下,通过在p型硅超层中制造n掺杂表面区域来形成p-n结。 在任一情况下,p-n结反向偏置用于电荷载流子的雪崩倍增。 在反向偏压工作条件下,APD中电场分布的最大值位于p-n结。 该最大值等于远离吸收区域的p型硅层的厚度。 吸收区域中的电场值主要取决于p型硅层的厚度和掺杂水平。 吸收区域中的电场值被可控地设定为在吸收区域中获得高的载流子速度而不引起载流子通道。
    • 5. 发明申请
    • PLANAR HETERO-INTERFACE PHOTODETECTOR
    • 平面异性接口光电转换器
    • US20020063303A1
    • 2002-05-30
    • US09730692
    • 2000-12-06
    • Nova Crystals, Inc.
    • Alexandre PauchardYu-Hwa Lo
    • H01L027/14
    • H01L31/1075H01L31/02327H01L31/1844H01L31/1852Y02E10/544
    • A planar avalanche photodetector (APD) is fabricated by forming a, for example, InGaAs absorption layer on a pnull-type semiconductor substrate, such as InP, and wafer-bonding to the absorption layer a second p-type semiconductor, such as Si, to form a multiplication layer. The layer thickness of the multiplication layer is substantially identical to that of the absorption layer. A region in a top surface of the p-type Si multiplication layer is doped nnull-type to form a carrier separation region and a high electric field in the multiplication region. The APD can further include a guard-ring to reduce leakage currents as well as a resonant mirror structure to provide wavelength selectivity. The planar geometry furthermore favors the integration of high-speed electronic circuits on the same substrate to fabricate monolithic optoelectronic transceivers.
    • 通过在诸如InP的p +型半导体衬底上形成例如InGaAs吸收层并且与吸收层晶片接合来制造平面雪崩光电检测器(APD),第二p型半导体例如Si, 以形成乘法层。 倍增层的层厚与吸收层基本相同。 p型Si倍增层的上表面的区域掺杂n +型,以在乘法区域中形成载流子分离区域和高电场。 APD还可以包括防护环以减少泄漏电流以及谐振反射镜结构以提供波长选择性。 平面几何形状还有利于将高速电子电路集成在同一衬底上以制造单片光电收发器。
    • 6. 发明申请
    • Semiconductor eutectic alloy metal (SEAM) technology for fabrication of compliant composite substrates and integration of materials
    • 半导体共晶合金金属(SEAM)技术,用于制造柔性复合基板和材料的集成
    • US20010052535A1
    • 2001-12-20
    • US09800401
    • 2001-03-05
    • Nova Crystals, Inc.
    • Zuhua ZhuTuoh-Bin NgYu-Hwa Lo
    • B23K031/02
    • B23K20/023
    • A method of semiconductor eutectic alloy metal (SEAM) technology for integration of heterogeneous materials and fabrication of compliant composite substrates takes advantage of eutectic properties of alloys. Sub1 and Sub2 are used to represent the two heterogeneous materials to be bonded or composed into a compliant composite substrate. For the purpose of fabricating compliant composite substrate, the first substrate material (Sub1) combines with the second substrate material (Sub2) to form a composite substrate that controls the stress in the epitaxial layers during cooling. The second substrate material (Sub2) controls the stress in the epitaxial layer grown thereon so that it is compressive during annealing. A joint metal (JM) with a melting point of Tm is chosen to offer variable joint stiffness at different temperatures. JM and Sub1 form a first eutectic alloy at a first eutectic temperature Teu1 while JM and Sub2 form a second eutectic alloy at a second eutectic temperature Teu2. Tm1 and Tm2 are the melting points of Sub1 and Sub2, respectively The following condition should be met: Tm1, Tm2>Tm>Teu1, Teu2. After cleaning of Sub1 and Sub2, JM is deposited on the bonding sides of Sub1 and Sub2. After preliminary bonding by applying force to press the bonding surfaces together at room temperature, high temperature bonding is subsequently performed, during which the temperature is ramped up to a temperature equal to or higher than Tm. During cooling, JM solidifies first, after which two eutectic alloys solidify.
    • 半导体共晶合金金属(SEAM)技术用于整合异质材料和制造合适的复合材料的方法利用了合金的共晶性能。 Sub1和Sub2用于表示待结合或组成合适的复合衬底的两种异质材料。 为了制造合适的复合衬底,第一衬底材料(Sub1)与第二衬底材料(Sub2)组合以形成控制冷却期间外延层中的应力的复合衬底。 第二衬底材料(Sub2)控制在其上生长的外延层中的应力,使得其在退火期间是压缩的。 选择熔点为Tm的接头金属(JM),以在不同的温度下提供可变接头刚度。 JM和Sub1在第一共晶温度Teu1下形成第一共晶合金,而JM和Sub2在第二共晶温度Teu2下形成第二共晶合金。 Tm1和Tm2分别为Sub1和Sub2的熔点。应满足以下条件:Tm1,Tm2> Tm> Teu1,Teu2。 在清洗Sub1和Sub2之后,JM沉积在Sub1和Sub2的粘合侧上。 在室温下通过施加力将结合面压合在一起进行初步接合之后,随后进行高温接合,在此期间温度升高至等于或高于Tm的温度。 在冷却过程中,首先固化,然后两个共晶合金固化。