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1. 发明授权

US07220482B2 Aligned fine particles, method for producing the same and device using the same 有权
标题翻译：对齐微粒，其制造方法及其使用方法
公开(公告)号：US07220482B2
公开(公告)日：2007-05-22
申请号：US10055667
申请日：2002-01-22
申请人： Norishisa Mino , Yasuhiro Kawawake , Kiyoyuki Morita , Shigeo Yoshii , Mutuaki Murakami , Osamu Kusumoto
发明人： Norishisa Mino , Yasuhiro Kawawake , Kiyoyuki Morita , Shigeo Yoshii , Mutuaki Murakami , Osamu Kusumoto
IPC分类号： G11B5/702 , G11B5/712
CPC分类号： B82Y30/00 , B05D1/185 , B82Y10/00 , B82Y40/00 , C01P2004/03 , C01P2004/62 , C01P2004/64 , C01P2004/86 , C01P2006/33 , C01P2006/42 , C09C3/12 , G11B5/712 , G11B5/74 , G11B5/746 , G11B5/82 , G11B5/84 , G11B2005/0002 , G11C11/14 , G11C11/16 , G11C11/5671 , G11C2216/08 , H01F1/0306 , H01F1/047 , H01F10/007 , H01F10/123 , H01F41/305 , H01L29/42324 , Y10T428/1114 , Y10T428/1193 , Y10T428/24388 , Y10T428/24893 , Y10T428/2991 , Y10T428/2995 , Y10T428/2998 , Y10T428/31667
摘要： The present invention provides aligned fine particles that are aligned on a substrate. An organic coating film is bonded to surfaces of the fine particles is formed on the surfaces of the fine particles. An organic coating film bonded to a surface of the substrate is formed on the surface of the substrate. The organic coating film on the surfaces of the fine particles is bonded to the organic coating film on the surface of the substrate, whereby the fine particles are immobilized and aligned on the substrate. Thus, it is possible to align the fine particles of a nanometer scale in a specific direction. When fine magnetic particles are used, a magnetic recording medium for high recording density can be obtained, and a high-density magnetic recording/reproducing apparatus can be provided.
摘要翻译：本发明提供了在衬底上对准的对准的细颗粒。在微细颗粒的表面上形成有机涂膜粘合到细颗粒的表面上。在基板的表面上形成有结合到基板表面的有机涂膜。微粒表面上的有机涂膜与基板表面上的有机涂膜接合，由此将微粒固定并在基板上取向。因此，可以在特定方向上对准纳米级的微粒。当使用精细的磁性颗粒时，可以获得用于高记录密度的磁记录介质，并且可以提供高密度磁记录/再现装置。

2. 发明授权

US06740928B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06740928B2
公开(公告)日：2004-05-25
申请号：US10350140
申请日：2003-01-24
申请人： Shigeo Yoshii , Kiyoshi Morimoto , Kiyoyuki Morita , Haruyuki Sorada
发明人： Shigeo Yoshii , Kiyoshi Morimoto , Kiyoyuki Morita , Haruyuki Sorada
IPC分类号： H01L29788
CPC分类号： B82Y10/00 , G11C13/02 , G11C13/025 , G11C16/0408 , G11C16/0466 , G11C2216/06 , H01L29/42332 , H01L29/7883
摘要： The semiconductor device of the present invention includes: particles or interface states for passing charge formed on a p-type silicon substrate via a barrier layer; and particles for holding charge formed above the charge-passing particles via another barrier layer. The charge-holding particles are different from the charge-passing particles in parameters such as the particle diameter, the capacitance, the electron affinity, and the sum of electron affinity and forbidden bandwidth, to attain swift charge injection and release as well as stable charge holding in the charge-holding particles.
摘要翻译：本发明的半导体器件包括：通过阻挡层使用于在p型硅衬底上形成的电荷的粒子或界面状态; 以及通过另一个阻挡层形成在电荷通过颗粒上方形成的电荷的颗粒。电荷保持粒子与粒径，电容，电子亲和力，电子亲和力和禁带宽度之和等参数不同于充电粒子，以获得快速的电荷注入和释放以及稳定的电荷保持在电荷保持颗粒中。

3. 发明授权

US06548825B1 Semiconductor device including barrier layer having dispersed particles 有权
标题翻译：包括具有分散粒子的阻挡层的半导体装置
公开(公告)号：US06548825B1
公开(公告)日：2003-04-15
申请号：US09587268
申请日：2000-06-05
申请人： Shigeo Yoshii , Kiyoshi Morimoto , Kiyoyuki Morita , Haruyuki Sorada
发明人： Shigeo Yoshii , Kiyoshi Morimoto , Kiyoyuki Morita , Haruyuki Sorada
IPC分类号： H01L310328
CPC分类号： B82Y10/00 , G11C13/02 , G11C13/025 , G11C16/0408 , G11C16/0466 , G11C2216/06 , H01L29/42332 , H01L29/7883
摘要： The semiconductor device of the present invention includes: particles or interface states for passing charge formed on a p-type silicon substrate via a barrier layer; and particles for holding charge formed above the charge-passing particles via another barrier layer. The charge-holding particles are different from the charge-passing particles in parameters such as the particle diameter, the capacitance, the electron affinity, and the sum of electron affinity and forbidden bandwidth, to attain swift charge injection and release as well as stable charge holding in the charge-holding particles.
摘要翻译：本发明的半导体器件包括：通过阻挡层使用于在p型硅衬底上形成的电荷的粒子或界面状态; 以及通过另一个阻挡层形成在电荷通过颗粒上方形成的电荷的颗粒。电荷保持粒子与粒径，电容，电子亲和力，电子亲和力和禁带宽度之和等参数不同于充电粒子，以获得快速的电荷注入和释放以及稳定的电荷保持在电荷保持颗粒中。

4. 发明申请

US20090187010A1 Method of arranging ferritin and method of arranging inorganic particles 有权
标题翻译：安排铁蛋白的方法和无机颗粒的排列方法
公开(公告)号：US20090187010A1
公开(公告)日：2009-07-23
申请号：US12320556
申请日：2009-01-29
申请人： Shigeo Yoshii , Kazuaki Nishio , Shinya Kumagai , Ichiro Yamashita
发明人： Shigeo Yoshii , Kazuaki Nishio , Shinya Kumagai , Ichiro Yamashita
IPC分类号： C07K17/00
CPC分类号： C07K14/47 , B82B1/00 , B82Y30/00
摘要： To provide a method of arranging ferritin by which a high rate of the number of the molecular film spots on which sole ferritin molecule was arranged in effect, with respect to total number of the molecular film spots provided for arranging ferritin (sole arrangement rate) is achieved is objected to. Specifically, in Fer8 ferritin having a sequence excluding 7 amino acids of from the second to the eighth, from an amino acid sequence (Fer0 sequence) translated from a naturally occurring DNA sequence, lysine at position 91 is substituted with glutamic acid.
摘要翻译：为了提供一种安排铁蛋白的方法，相对于提供用于安排铁蛋白的总分子膜点数（单独排列速率），通过该铁蛋白排列高分子膜斑点的数量，单个铁蛋白分子排列有效的方法是：实现是反对的。具体而言，在来自第二至第八的7个氨基酸序列的Fer8铁蛋白中，从天然存在的DNA序列翻译的氨基酸序列（Fer0序列）中，91位的赖氨酸被谷氨酸取代。

5. 发明授权

US07419529B2 Method of forming fine particle array on substrate and semiconductor element 有权
标题翻译：在基板和半导体元件上形成微粒阵列的方法
公开(公告)号：US07419529B2
公开(公告)日：2008-09-02
申请号：US11284910
申请日：2005-11-23
申请人： Shigeo Yoshii , Michihito Ueda , Nozomu Matsukawa , Ichiro Yamashita
发明人： Shigeo Yoshii , Michihito Ueda , Nozomu Matsukawa , Ichiro Yamashita
IPC分类号： B22F9/20
CPC分类号： B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： An object of the present invention is to provide a method of forming fine particles on a substrate in which reoxidization of reduced fine particles is suppressed. Reduced fine particles (FeO fine particles) are formed by embedding metal oxide fine particles (Fe2O3 fine particles) fixed on a p type silicon semiconductor substrate into a silicon oxidized film, and carrying out a heat treatment in a reducing gas atmosphere. Presence of the silicon oxidized film enables suppression of reoxidization of the reduced fine particles (FeO fine particles) due to exposure to the ambient air.
摘要翻译：本发明的目的是提供一种在抑制还原的微粒的再氧化的基板上形成微粒的方法。通过将固定在p型硅半导体衬底上的金属氧化物微粒（Fe 2 O 3 O 3微粒）嵌入到硅氧化膜中而形成还原的微粒（FeO微粒），并在还原气体气氛中进行热处理。硅氧化膜的存在能够抑制由于暴露于环境空气而导致的还原的微粒（FeO微粒）的再氧化。

6. 发明授权

US6087725A Low barrier ohmic contact for semiconductor light emitting device 失效
标题翻译：半导体发光器件的低阻挡欧姆接触
公开(公告)号：US6087725A
公开(公告)日：2000-07-11
申请号：US161498
申请日：1998-09-28
申请人： Shigeo Yoshii , Yoichi Sasai , Satoshi Kamiyama , Tohru Saitoh , Takashi Nishikawa , Ryoko Miyanaga
发明人： Shigeo Yoshii , Yoichi Sasai , Satoshi Kamiyama , Tohru Saitoh , Takashi Nishikawa , Ryoko Miyanaga
IPC分类号： H01L33/28 , H01L33/40 , H01L33/00
CPC分类号： H01L33/40 , H01L33/28
摘要： On a substrate of n-type GaAs, an n-type cladding layer of n-type Zn.sub.0.9 Mg.sub.0.1 S.sub.0.13 Se.sub.0.87, an n-type light guiding layer of n-type ZnS.sub.0.06 Se.sub.0.94, an active layer of ZnCdSe and a p-type light guiding layer of p-type ZnS.sub.0.06 Se.sub.0.94 are successively formed. On the p-type light guiding layer, a p-type contact structure is formed. The p-type contact structure includes a first layer of p-type ZnS.sub.0.31 Se.sub.0.54 Te.sub.0.15, a second layer of ZnS.sub.0.47 Se.sub.0.28 Te.sub.0.25, a third layer of p-type ZnS.sub.0.65 Te.sub.0.35, a fourth layer of p-type ZnS.sub.0.5 Te.sub.0.5 and a fifth layer of p-type ZnTe.
摘要翻译：在n型GaAs的衬底上，n型Zn0.9Mg0.1S0.13Se0.87的n型覆层，n型ZnS0.06Se0.94的n型导光层，n型ZnS0.06Se0.94的有源层 ZnCdSe和p型ZnS0.06Se0.94的p型导光层依次形成。在p型导光层上形成p型接触结构。 p型接触结构包括第一层p型ZnS0.31Se0.54Te0.15，第二层ZnS0.47Se0.28Te0.25，第三层p型ZnS0.65Te0.35，第四层的p型ZnS0.5Te0.5和第五层p型ZnTe。

7. 发明申请

US20120058490A1 METHOD FOR DETECTING AN ANTIGEN 有权
标题翻译：检测抗原的方法
公开(公告)号：US20120058490A1
公开(公告)日：2012-03-08
申请号：US13296879
申请日：2011-11-15
申请人： Kazuaki NISHIO , Nozomu Matsukawa , Shigeo Yoshii
发明人： Kazuaki NISHIO , Nozomu Matsukawa , Shigeo Yoshii
IPC分类号： G01N27/00
CPC分类号： G01N33/54306 , C12Q1/26
摘要： Provided is a method for detecting an antigen without use of a labeled-antibody. A support having an antibody and a multi-copper oxidase CueO immobilized thereon is brought into contact with a first buffer solution containing the antigen, a current is measured by a potentiostat method using the support and a second buffer solution, and when the measured current is greater than or equal to 1.5×(blank value), it is determined that the antigen exists. The second buffer solution contains a substrate of the CueO and has an ionic strength falling within a range of not less than 0.3 mM and not more than 1.0 mM.
摘要翻译：提供了不使用标记抗体来检测抗原的方法。使具有固定在其上的抗体和多铜氧化酶CueO的载体与含有抗原的第一缓冲溶液接触，通过使用载体和第二缓冲溶液的恒电位法测量电流，并且当测量的电流为大于或等于1.5×（空白值），则确定存在抗原。第二缓冲溶液含有CueO的底物，离子强度在0.3mM以上1.0mM以下的范围内。

8. 发明申请

US20080108227A1 Method for producing single electron semiconductor element 有权
标题翻译：单电子半导体元件的制造方法
公开(公告)号：US20080108227A1
公开(公告)日：2008-05-08
申请号：US11878691
申请日：2007-07-26
申请人： Shinya Kumagai , Shigeo Yoshii , Nozomu Matsukawa , Ichiro Yamashita
发明人： Shinya Kumagai , Shigeo Yoshii , Nozomu Matsukawa , Ichiro Yamashita
IPC分类号： H01L21/28
CPC分类号： H01L29/7613 , B82Y10/00 , H01L29/66439 , H01L49/006 , Y10S438/962 , Y10S977/773
摘要： The present invention provides a method for production of a single electron semiconductor element (SET) in which a quantum dot is selectively arranged in a nano gap between fine electrodes, whereby the product yield is significantly improved, leading to excellent practical applicability. The method for production of SET of the present invention is characterized in that a solution containing ferritin including a metal or semiconductor particle therein, and a nonionic surfactant is dropped on a substrate having a source electrode and a drain electrode formed by laminating a titanium film and a film of a metal other than titanium, whereby the ferritin is selectively arranged in a nano gap between the source electrode/drain electrode. In the method for production of SET of the present invention, the metal or semiconductor particle can be fixed as a quantum dot at a suitable position in the nano gap between the source electrode/drain electrode following decomposition of ferritin, and in addition, formation of unnecessary quantum dot can be suppressed.
摘要翻译：本发明提供一种单电子半导体元件（SET）的制造方法，其中量子点选择性地排列在细电极之间的纳米间隙中，从而显着提高了产品产率，从而实现了优异的实用性。本发明的SET的制造方法的特征在于，将含有金属或半导体粒子的铁蛋白和非离子表面活性剂的溶液滴落在具有源极电极和漏电极的基板上，所述源极和漏极通过层叠钛膜和除钛以外的金属的膜，由此铁素体选择性地排列在源电极/漏电极之间的纳米间隙中。在本发明的SET的制造方法中，金属或半导体粒子可以在铁蛋白分解后的源电极/漏电极之间的纳米间隙的适当位置作为量子点固定，另外，形成可以抑制不必要的量子点。

9. 发明申请

US20060231862A1 Ballistic semiconductor device 失效
标题翻译：弹道半导体器件
公开(公告)号：US20060231862A1
公开(公告)日：2006-10-19
申请号：US10542063
申请日：2004-04-14
申请人： Nobuyuki Otsuka , Koichi Mizuno , Shigeo Yoshii , Asamira Suzuki
发明人： Nobuyuki Otsuka , Koichi Mizuno , Shigeo Yoshii , Asamira Suzuki
IPC分类号： H01L31/00
CPC分类号： H01L29/7371 , H01L29/2003 , H01L29/7376
摘要： A ballistic semiconductor device of the present invention comprises a n-type emitter layer (102), a base layer (305) made of n-type InGaN, a n-type collector layer (307), an emitter barrier layer (103) interposed between the emitter layer (102) and the base layer (305) and having a band gap larger than that of the base layer (305), and a collector barrier layer (306) interposed between the base layer (305) and the collector layer (307) and having a band gap larger than that of the base layer (305), and operates at 10 GHz or higher.
摘要翻译：本发明的弹道半导体器件包括n型发射极层（102），由n型InGaN制成的基极层（305），n型集电极层（307），发射极阻挡层（103）在发射极层（102）和基极层（305）之间具有比基底层（305）的带隙大的带隙的集电极阻挡层（306），并且位于基极层（305）和集电极层（307），并且具有比基底层（305）的带隙大的带隙，并且在10GHz或更高频率下工作。

10. 发明授权

US06903383B2 Semiconductor device having a high breakdown voltage for use in communication systems 失效
标题翻译：具有用于通信系统的高击穿电压的半导体器件
公开(公告)号：US06903383B2
公开(公告)日：2005-06-07
申请号：US10343097
申请日：2001-11-21
申请人： Toshiya Yokogawa , Asamira Suzuki , Masahiro Deguchi , Shigeo Yoshii , Hiroyuki Furuya
发明人： Toshiya Yokogawa , Asamira Suzuki , Masahiro Deguchi , Shigeo Yoshii , Hiroyuki Furuya
IPC分类号： H01L21/8252 , H01L27/06 , H01L29/20 , H01L29/778 , H03F3/60 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L27/0605 , H01L21/8252 , H01L29/2003 , H01L29/7785 , H03F3/601 , H03F2200/294
摘要： A HEMT has an InAlAs layer (202), an InGaAs layer (203), a multiple δ-doped InAlAs layer (204) composed of n-type doped layers (204a) and undoped layers (204b) which are alternately stacked, an InP layer (205), a Schottky gate electrode (210), a source electrode (209a), and a drain electrode (209b) on an InP substrate (201). When a current flows in a region (channel region) of the InGaAs layer (203) adjacent the interface between the InGaAs layer (203) and the multiple δ-doped InAlAs layer (204), a breakdown voltage in the OFF state can be increased, while resistance to the movement of carriers passing through the multiple δ-doped InAlAs layer (204) as a carrier supplying layer is reduced.
摘要翻译： HEMT具有InAlAs层（202），InGaAs层（203），由交替层叠的n型掺杂层（204a）和未掺杂层（204b）构成的多重δ掺杂InAlAs层（204） InP层（205），肖特基栅电极（210），源极电极（209a）和漏极电极（209b）。当电流在与InGaAs层（203）和多重δ掺杂的InAlAs层（204）之间的界面相邻的InGaAs层（203）的区域（沟道区）中流动时，可以增加关断状态下的击穿电压，同时抵抗通过作为载流子供给层的多个δ-掺杂InAlAs层（204）的载流子的移动。

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