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1. 发明授权

US5778202A Ring bus multiprocessor system and processor boards for constituting the same 失效
标题翻译：环形总线多处理器系统和处理器板构成相同
公开(公告)号：US5778202A
公开(公告)日：1998-07-07
申请号：US662445
申请日：1996-06-10
申请人： Norihiko Kuroishi , Tetsuro Kawata , Kenichi Kawauchi , Nobuaki Miyakawa , Reiji Aibara , Mitsumasa Koyanagi
发明人： Norihiko Kuroishi , Tetsuro Kawata , Kenichi Kawauchi , Nobuaki Miyakawa , Reiji Aibara , Mitsumasa Koyanagi
IPC分类号： G06F15/173 , G06F13/40 , G06F13/00 , G06F13/38
CPC分类号： G06F13/4095
摘要： A ring bus multiprocessor system whose processors are laid out and connected in such a manner that the system is enhanced in stability and performance, is easy to modify in scale, and is lowered in manufacturing cost. On a processor board, processors are serially connected by communication buses to form a processor group. Each processor board may have an even-numbered plurality of processor groups mounted thereon. A plurality of processor boards are laid out in parallel and are interconnected between adjacent boards by means of inter-processor communication buses. Each of the odd-numbered processor groups is connected from one board to the next up to the most downstream board where the connection is looped back to the adjacent even-numbered processor group. In turn, the even-numbered processor group is connected from one board to the next back to the most upstream board where the connection is again looped back to the adjacent odd-numbered processor group, and so on, whereby a ring bus arrangement is formed.
摘要翻译：一种环形总线多处理器系统，其处理器以这样的方式布置和连接，使得系统的稳定性和性能得到提高，容易在规模上进行修改，并降低制造成本。在处理器板上，处理器通过通信总线串联连接，形成处理器组。每个处理器板可以具有安装在其上的偶数个多个处理器组。多个处理器板并联布置并且通过处理器间通信总线在相邻板之间互连。每个奇数处理器组从一个板连接到下一个板到下游板，其中连接被环回到相邻的偶数处理器组。反过来，偶数处理器组从一个板连接到下一个回到最上游板，其中连接再次环回到相邻的奇数处理器组，依此类推，形成环形总线布置。

2. 发明授权

US06525415B2 Three-dimensional semiconductor integrated circuit apparatus and manufacturing method therefor 失效
标题翻译：三维半导体集成电路装置及其制造方法
公开(公告)号：US06525415B2
公开(公告)日：2003-02-25
申请号：US09745874
申请日：2000-12-26
申请人： Mitsumasa Koyanagi , Yasunori Okano , Nobuaki Miyakawa
发明人： Mitsumasa Koyanagi , Yasunori Okano , Nobuaki Miyakawa
IPC分类号： H01L2302
CPC分类号： H01L27/0688 , H01L21/8221 , H01L23/5385 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/13109 , H01L2224/13144 , H01L2224/16145 , H01L2224/2919 , H01L2224/73204 , H01L2224/81193 , H01L2224/9202 , H01L2225/06513 , H01L2225/06541 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2924/01049 , H01L2924/00014
摘要： A three-dimensional semiconductor integrated circuit apparatus which permits ready electrical connection and is resistant to deformation and easy to fabricate and a manufacturing method therefor are provided. A second semiconductor substrate is stacked over a third semiconductor substrate, and a first semiconductor substrate is stacked over the second semiconductor substrate. A second integrated circuit is formed over the surface layer of the second semiconductor substrate, and the integrated circuit side of the second semiconductor substrate is bonded to the integrated circuit side of the first semiconductor substrate, resulting in the electrical connection of the first integrated circuit formed over the surface layer of the first semiconductor substrate and the second integrated circuit. In the second semiconductor substrate is formed embedded wiring of which one end is electrically connected to the second integrated circuit and the other end is exposed from the back side, and the third integrated circuit formed over the surface layer of the third semiconductor substrate and the second integrated circuit are electrically connected to the embedded wiring.
摘要翻译：本发明提供了能够容易地进行电连接并且耐变形且易于制造的三维半导体集成电路装置及其制造方法。第二半导体衬底层叠在第三半导体衬底上，并且第一半导体衬底堆叠在第二半导体衬底上。第二集成电路形成在第二半导体衬底的表面层上，并且第二半导体衬底的集成电路侧接合到第一半导体衬底的集成电路侧，导致形成的第一集成电路的电连接在第一半导体衬底和第二集成电路的表面层上。在第二半导体基板中形成嵌入布线，其一端电连接到第二集成电路，另一端从背面暴露，并且第三集成电路形成在第三半导体基板的表面层上，第二集成电路集成电路电连接到嵌入式布线。

3. 发明授权

US08349652B2 Method and apparatus for manufacturing three-dimensional integrated circuit 有权
标题翻译：制造三维集成电路的方法和装置
公开(公告)号：US08349652B2
公开(公告)日：2013-01-08
申请号：US13258664
申请日：2010-03-10
申请人： Mitsumasa Koyanagi , Takafumi Fukushima , Masahiko Sugiyama
发明人： Mitsumasa Koyanagi , Takafumi Fukushima , Masahiko Sugiyama
IPC分类号： H01L21/50
CPC分类号： H01L21/50 , H01L21/6835 , H01L21/76898 , H01L23/13 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/95 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2221/68318 , H01L2221/6834 , H01L2221/68354 , H01L2221/68368 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/06182 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13184 , H01L2224/1403 , H01L2224/14181 , H01L2224/81193 , H01L2224/81801 , H01L2224/83002 , H01L2224/83005 , H01L2224/83143 , H01L2224/83193 , H01L2224/83896 , H01L2224/921 , H01L2224/95001 , H01L2224/95146 , H01L2225/06513 , H01L2225/06541 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/15788 , Y10T156/1798 , H01L2924/00014 , H01L2924/00
摘要： There is provided a three-dimensional integrated circuit manufacturing method for temporarily attaching a chip to a transcription substrate, and securely detaching the chip from the transcription substrate when the chip is transferred to a supporting substrate. When a chip is temporarily attached to a transcription substrate, by evaporating a liquid existing between the chip and the transcription substrate, the solids of the chip and the transcription substrate can be attached to each other. Accordingly, the chip can be temporarily attached to the transcription substrate so as not to be deviated from its own position. Further, by setting adhesive strength between the chip and a supporting substrate to be higher than that between the chip and the transcription substrate, the chip can be securely detached from the transcription substrate when the chip is transferred from the transcription substrate to the supporting substrate.
摘要翻译：提供了一种用于将芯片临时附接到转录底物的三维集成电路制造方法，并且当芯片被转移到支撑衬底时，可靠地将芯片从转录衬底上分离。当芯片临时连接到转录底物时，通过蒸发芯片和转录底物之间的液体，芯片和转录底物的固体可以彼此附着。因此，芯片可以临时安装到转录基片上，以便不会偏离其本身的位置。此外，通过将芯片和支撑基板之间的粘合强度设置为高于芯片和转录基板之间的粘合强度，当芯片从转录基板转移到支撑基板时，可以将芯片从转录基板上牢固地分离。

4. 发明授权

US08283208B2 Method and apparatus for fabricating integrated circuit device using self-organizing function 有权
标题翻译：使用自组织功能制造集成电路器件的方法和装置
公开(公告)号：US08283208B2
公开(公告)日：2012-10-09
申请号：US11813032
申请日：2005-12-28
申请人： Mitsumasa Koyanagi
发明人： Mitsumasa Koyanagi
IPC分类号： H01L21/00
CPC分类号： H01L21/6835 , H01L21/568 , H01L21/6836 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68313 , H01L2221/68327 , H01L2221/68354 , H01L2221/68363 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13147 , H01L2224/13184 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/16 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/32145 , H01L2224/73104 , H01L2224/73204 , H01L2224/73259 , H01L2224/75 , H01L2224/7598 , H01L2224/78743 , H01L2224/81097 , H01L2224/81143 , H01L2224/81193 , H01L2224/81201 , H01L2224/81801 , H01L2224/81907 , H01L2224/83193 , H01L2224/838 , H01L2224/83907 , H01L2224/95001 , H01L2224/95145 , H01L2224/95146 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/10253 , H01L2924/12043 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/15788 , H01L2224/81 , H01L2224/83 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/01031
摘要： In a method of fabricating an integrated circuit device having a three-dimensional stacked structured, the step of fixing many chip-shaped semiconductor circuits to a support substrate or a circuit layer with a predetermined layout can be performed easily and efficiently with a desired accuracy. Temporary adhesion portions 12b of semiconductor chips 13 are temporarily adhered to corresponding temporary adhesion regions 72a of a carrier substrate 73a by way of water films 81. The carrier substrate 73a is then pressed toward a support substrate or a desired circuit layer, thereby contacting connecting portions 12 of the chips 13 on the carrier substrate 73a with corresponding predetermined positions on the support substrate or a circuit layer. Thereafter, by fixing the connecting portions 12 to the predetermined positions, the chips 13 are attached to the support substrate or the circuit layer with a desired layout.
摘要翻译：在制造具有三维堆叠结构的集成电路器件的方法中，可以以期望的精度容易且有效地执行将许多芯片形半导体电路固定到支撑衬底或具有预定布局的电路层的步骤。半导体芯片13的临时粘合部分12b通过水膜81临时粘附到载体基板73a的相应的临时粘合区域72a上。然后将载体基板73a压向支撑基板或所需的电路层，从而接触连接部分载体基板73a上的芯片13的12个，在支撑基板或电路层上具有对应的预定位置。此后，通过将连接部分12固定到预定位置，芯片13以期望的布局附接到支撑基板或电路层。

5. 发明申请

US20060057845A1 Method of forming nickel-silicon compound, semiconductor device, and semiconductor device manufacturing method 审中-公开
标题翻译：形成镍硅化合物的方法，半导体器件和半导体器件的制造方法
公开(公告)号：US20060057845A1
公开(公告)日：2006-03-16
申请号：US11207562
申请日：2005-08-19
申请人： Mitsumasa Koyanagi , Hiroyuki Kurino , Toshiaki Kurino , Jeoung Shim
发明人： Mitsumasa Koyanagi , Hiroyuki Kurino , Toshiaki Kurino , Jeoung Shim
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/78
摘要： There is disclosed a method of forming a nickel film on a silicon substrate or a silicon film, followed by applying an annealing process such that a final annealing temperature TH is in the range of 500° C.
摘要翻译：公开了在硅衬底或硅膜上形成镍膜的方法，然后进行退火处理，使得最终退火温度TH在500℃的范围内。

6. 发明授权

US4891326A Semiconductor device and a process for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US4891326A
公开(公告)日：1990-01-02
申请号：US206896
申请日：1988-06-08
申请人： Mitsumasa Koyanagi
发明人： Mitsumasa Koyanagi
IPC分类号： H01L21/265 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L21/823864 , H01L21/76202 , H01L27/0928 , H01L29/78
摘要： A process for fabricating a semiconductor device having n-channel and p-channel MOSFET's. Each MOSFET has a pair of side walls that are simultaneously formed on both sides of the gate electrode. The n-channel MOSFET has source and drain regions consisting of a low-concentration region formed by implanting ions using the gate electrode as a mask, and a high-concentration region formed by implanting ions using the gate electrode and side walls as masks. The p-channel MOSFET has source and drain regions consisting of high-concentration regions formed by implanting ions using the gate electrode and side walls as masks.
摘要翻译：一种制造具有n沟道和p沟道MOSFET的半导体器件的工艺。每个MOSFET具有同时形成在栅极两侧的一对侧壁。 n沟道MOSFET具有源极和漏极区，其由通过使用栅电极注入离子作为掩模形成的低浓度区域和通过使用栅电极和侧壁作为掩模注入离子而形成的高浓度区域组成。 p沟道MOSFET具有源极和漏极区域，其由通过使用栅电极和侧壁作为掩模注入离子形成的高浓度区域组成。

7. 发明申请

US20120021563A1 METHOD AND APPARATUS FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT 有权
标题翻译：制造三维集成电路的方法和装置
公开(公告)号：US20120021563A1
公开(公告)日：2012-01-26
申请号：US13258664
申请日：2010-03-10
申请人： Mitsumasa Koyanagi , Takafumi Fukushima , Masahiko Sugiyama
发明人： Mitsumasa Koyanagi , Takafumi Fukushima , Masahiko Sugiyama
IPC分类号： H01L21/50 , B32B37/14 , B32B38/00 , B32B37/12
CPC分类号： H01L21/50 , H01L21/6835 , H01L21/76898 , H01L23/13 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/95 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2221/68318 , H01L2221/6834 , H01L2221/68354 , H01L2221/68368 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/06182 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13184 , H01L2224/1403 , H01L2224/14181 , H01L2224/81193 , H01L2224/81801 , H01L2224/83002 , H01L2224/83005 , H01L2224/83143 , H01L2224/83193 , H01L2224/83896 , H01L2224/921 , H01L2224/95001 , H01L2224/95146 , H01L2225/06513 , H01L2225/06541 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/15788 , Y10T156/1798 , H01L2924/00014 , H01L2924/00
摘要： There is provided a three-dimensional integrated circuit manufacturing method for temporarily attaching a chip to a transcription substrate, and securely detaching the chip from the transcription substrate when the chip is transferred to a supporting substrate. When a chip is temporarily attached to a transcription substrate, by evaporating a liquid existing between the chip and the transcription substrate, the solids of the chip and the transcription substrate can be attached to each other. Accordingly, the chip can be temporarily attached to the transcription substrate so as not to be deviated from its own position. Further, by setting adhesive strength between the chip and a supporting substrate to be higher than that between the chip and the transcription substrate, the chip can be securely detached from the transcription substrate when the chip is transferred from the transcription substrate to the supporting substrate.
摘要翻译：提供了一种用于将芯片临时附接到转录底物的三维集成电路制造方法，并且当芯片被转移到支撑衬底时，可靠地将芯片从转录衬底上分离。当芯片临时连接到转录底物时，通过蒸发芯片和转录底物之间的液体，芯片和转录底物的固体可以彼此附着。因此，芯片可以临时安装到转录基片上，以便不会偏离其本身的位置。此外，通过将芯片和支撑基板之间的粘合强度设置为高于芯片和转录基板之间的粘合强度，当芯片从转录基板转移到支撑基板时，可以将芯片从转录基板上牢固地分离。

8. 发明申请

US20070155099A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING EXCELLENT CHARGE RETENTION AND MANUFACTURING PROCESS OF THE SAME 审中-公开
标题翻译：具有优异充电保持性及其制造工艺的非挥发性半导体存储器件
公开(公告)号：US20070155099A1
公开(公告)日：2007-07-05
申请号：US11685077
申请日：2007-03-12
申请人： Masaaki Takata , Mitsumasa Koyanagi
发明人： Masaaki Takata , Mitsumasa Koyanagi
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/42332 , Y10S977/943
摘要： There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult to be achieved due to the essential problem. In order to solve the above problem, in the nonvolatile semiconductor memory device of the present invention, a material having large work function or large electron affinity or a material having a work function close to that of semiconductor substrate or of a control gate, is employed for a floating gate retaining charges. Further, an amorphous material having small electron affinity for an insulating matrix is used. Further, at a time of deposition of charge retention layer, the supply ratio of the nano-particle material and the insulating matrix material, such as the mixture ratio of materials of both phases in a target in a sputtering method, is adjusted. By these methods, the charge retention characteristic of the floating-gate type nonvolatile semiconductor memory device can be improved, and the above-mentioned problem of the nonvolatile semiconductor memory device can be solved.
摘要翻译：在常规的Si型浮栅型非易失性半导体存储器件中存在由于Si的电子亲和力不足而导致的电荷保持特性低的问题，因此存储器性能的改善，例如存储器单元的缩小和提高运行速度，由于基本问题而难以实现。为了解决上述问题，在本发明的非易失性半导体存储器件中，使用具有大功函数或大电子亲和性的材料或具有接近半导体衬底或控制栅的功函数的材料为浮门保留费用。此外，使用对绝缘基体具有小的电子亲和力的无定形材料。此外，在电荷保持层的沉积时，调整纳米粒子材料和绝缘基体材料的供给比例，例如溅射法中的靶中的两相的材料的混合比例。通过这些方法，可以提高浮栅型非易失性半导体存储器件的电荷保持特性，并且可以解决上述非易失性半导体存储器件的问题。

9. 发明申请

US20060118853A1 Nonvolatile semiconductor memory device having excellent charge retention and manufacturing process of the same 失效
标题翻译：非易失性半导体存储器件具有优异的电荷保持率及其制造工艺
公开(公告)号：US20060118853A1
公开(公告)日：2006-06-08
申请号：US11003421
申请日：2004-12-06
申请人： Masaaki Takata , Mitsumasa Koyanagi
发明人： Masaaki Takata , Mitsumasa Koyanagi
IPC分类号： H01L29/76
CPC分类号： H01L29/42332 , Y10S977/943
摘要： There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult to be achieved due to the essential problem. In order to solve the above problem, in the nonvolatile semiconductor memory device of the present invention, a material having large work function or large electron affinity or a material having a work function close to that of semiconductor substrate or of a control gate, is employed for a floating gate retaining charges. Further, an amorphous material having small electron affinity for an insulating matrix is used. Further, at a time of deposition of charge retention layer, the supply ratio of the nano-particle material and the insulating matrix material, such as the mixture ratio of materials of both phases in a target in a sputtering method, is adjusted. By these methods, the charge retention characteristic of the floating-gate type nonvolatile semiconductor memory device can be improved, and the above-mentioned problem of the nonvolatile semiconductor memory device can be solved.
摘要翻译：在常规的Si型浮栅型非易失性半导体存储器件中存在由于Si的电子亲和力不足而导致的电荷保持特性低的问题，因此存储器性能的改善，例如存储器单元的缩小和增加运行速度，由于基本问题而难以实现。为了解决上述问题，在本发明的非易失性半导体存储器件中，使用具有大功函数或大电子亲和性的材料或具有接近半导体衬底或控制栅的功函数的材料为浮门保留费用。此外，使用对绝缘基体具有小的电子亲和力的无定形材料。此外，在电荷保持层的沉积时，调整纳米粒子材料和绝缘基体材料的供给比例，例如溅射法中的靶中的两相的材料的混合比例。通过这些方法，可以提高浮栅型非易失性半导体存储器件的电荷保持特性，并且可以解决上述非易失性半导体存储器件的问题。

10. 发明申请

US20060115943A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING LOW DIELECTRIC CONSTANT MATERIAL FILM 有权
标题翻译：使用低介电常数材料薄膜制作半导体器件的方法
公开(公告)号：US20060115943A1
公开(公告)日：2006-06-01
申请号：US11275733
申请日：2006-01-26
申请人： Mitsumasa Koyanagi
发明人： Mitsumasa Koyanagi
IPC分类号： H01L21/8234
CPC分类号： H01L21/84 , H01L21/76898 , H01L21/8221 , H01L27/0688 , H01L27/12 , H01L29/42384 , H01L29/66772 , H01L29/78603 , H01L29/78648 , H01L2224/2919 , H01L2224/32145 , H01L2924/00014
摘要： The semiconductor device is capable of coping with speedup of operation using a low dielectric constant material film other than silicon. The base (10) formed by the substrate (11) and the low dielectric constant material film (12) whose relative dielectric constant is lower than silicon is provided. The semiconductor element layer including the MOS transistor (30) is adhered onto the surface of the base (10) for stacking. The transistor (30) is formed by using the island-shaped single-crystal Si film (31) and buried in the insulator films (15), (16) and (17). The multilayer wiring structure (18) is formed on the semiconductor element layer and is electrically connected to the transistor (30). The electrode (20) functioning as a return path for the signals is formed on the back surface of the base (10). Instead of forming the electrode (20) on the base (10), the electrodes (20A) may be arranged on the back surface of the base (10A), configuring the base (10A) as an interposer.
摘要翻译：半导体器件能够使用除硅以外的低介电常数材料膜来应对加速操作。设置由基板（11）形成的基板（10）和相对介电常数低于硅的低介电常数材料薄膜（12）。包括MOS晶体管（30）的半导体元件层粘附到基底（10）的表面上以进行堆叠。晶体管（30）通过使用岛状单晶硅膜（31）形成并埋入绝缘膜（15），（16）和（17）中。多层布线结构（18）形成在半导体元件层上并与晶体管（30）电连接。用作信号返回路径的电极（20）形成在基座（10）的背面上。代替在基座（10）上形成电极（20），电极（20A）可以布置在基座（10A）的后表面上，构成基座（10A）作为插入件。

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