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1. 发明授权

US08354730B2 Manufacturing method of semiconductor device and semiconductor device 失效
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US08354730B2
公开(公告)日：2013-01-15
申请号：US11997436
申请日：2006-08-25
申请人： Satoshi Moriya , Toshio Saito , Goichi Yokoyama , Tsuyoshi Fujiwara , Hidenori Sato , Nobuaki Miyakawa
发明人： Satoshi Moriya , Toshio Saito , Goichi Yokoyama , Tsuyoshi Fujiwara , Hidenori Sato , Nobuaki Miyakawa
IPC分类号： H01L21/70
CPC分类号： H01L21/76898 , H01L21/2007 , H01L21/76232 , H01L21/8221 , H01L23/481 , H01L24/94 , H01L2224/2518 , H01L2924/01004 , H01L2924/04941 , H01L2924/1305 , H01L2924/14 , H01L2924/00
摘要： A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS•FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.
摘要翻译：提供了通过将形成在各个半导体衬底的半导体芯片上的多个半导体衬底和电连接集成电路粘合在一起而获得所需集成电路的结构，并且穿透电极穿透每个半导体衬底的主表面和后表面分离基板和分离穿透电极的穿透分离部分。因此，在半导体衬底上形成用于形成穿透分离部分的绝缘沟槽部分之后，形成MIS·FET，然后形成用于形成穿透电极的导电沟槽部分。因此，可以提高具有三维结构的半导体器件的元件特性。

2. 发明授权

US08049296B2 Semiconductor wafer 有权
标题翻译：半导体晶圆
公开(公告)号：US08049296B2
公开(公告)日：2011-11-01
申请号：US12718061
申请日：2010-03-05
申请人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
发明人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
IPC分类号： H01L29/00
CPC分类号： H01L25/117 , H01L21/6835 , H01L21/76898 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/81139 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/01019 , H01L2924/01037 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.
摘要翻译：在衬底上形成有从衬底的主表面延伸到所需深度的深度隔离沟槽，其中埋置有绝缘膜以形成通过隔离部分。随后，在衬底的主表面上形成MOSFET之后，在衬底的主表面上沉积层间绝缘膜。然后，在由通过隔离部包围的区域中形成从层间绝缘膜的上表面延伸至衬底厚度内的深度的深导电沟槽。随后，将导电膜埋在深导电沟槽中以形成通过互连部分。然后，在将基板的下表面研磨抛光至不暴露通过隔离部分和通过互连部分的程度之后，进行湿法蚀刻，使其暴露于每个通过隔离部分的下部的部分，以及直通互连部分。

3. 发明授权

US08022525B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08022525B2
公开(公告)日：2011-09-20
申请号：US12369456
申请日：2009-02-11
申请人： Takanori Maebashi , Nobuaki Miyakawa
发明人： Takanori Maebashi , Nobuaki Miyakawa
IPC分类号： H01L23/02 , H01L21/44
CPC分类号： H01L23/481 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2224/05001 , H01L2224/11 , H01L2224/13 , H01L2224/13009 , H01L2224/13022 , H01L2224/16 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2225/06555 , H01L2225/06575 , H01L2924/1305 , H01L2924/13091 , H01L2924/19041 , H01L2924/00
摘要： A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer includes an lamination surface to which another wafer is laminated and a substrate having an element formed thereon; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another wafer so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from a region which exposes the substrate on the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit, and is formed of the same material as the substrate to protrude from the lamination surface with a height equal to the length of a gap between the lamination surfaces of wafers facing each other is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion.
摘要翻译：半导体器件具有彼此层叠的多个晶片，其中：每个晶片包括层叠另一晶片的层叠表面和形成有元件的衬底; 层叠表面设置有电连接到所述另一晶片的电信号连接部分，以形成半导体电路; 电信号连接部中的至少一个彼此面对的是突出的连接部，其从层叠面上露出基板的区域突出; 和与半导体电路绝缘的加强突出部分，并且由与层叠表面突出的相同材料形成，其高度等于彼此面对的晶片的层叠表面之间的间隙的长度在突起连接部未设置在形成有突出连接部的层叠面上的区域中。

4. 发明授权

US07664714B2 Neural network element with reinforcement/attenuation learning 有权
标题翻译：具有加强/衰减学习的神经网络元素
公开(公告)号：US07664714B2
公开(公告)日：2010-02-16
申请号：US11255895
申请日：2005-10-21
申请人： Hiroshi Tsujino , Nobuaki Miyakawa , Gen Matsumoto , Ryoji Noyori, legal representative
发明人： Hiroshi Tsujino , Nobuaki Miyakawa , Gen Matsumoto
IPC分类号： G06N3/02
CPC分类号： G06N3/08 , G06N3/049
摘要： A neural network element, outputting an output signal in response to a plurality of input signals, comprises a history memory for accumulating and storing the plurality of input signals in a temporal order as history values. It also includes an output module for outputting the output signal when an internal state exceeds a predetermined threshold value, the internal state being based on a sum of the product of a plurality of input signals and corresponding coupling coefficients. The history values depend on change of the internal state. The neural network element is configured to subtract a predetermined value from the internal state immediately after the output module fires and performs learning for reinforcing or attenuating the coupling coefficient according to the history values after the output module fires.
摘要翻译：输出响应于多个输入信号的输出信号的神经网络元件包括用于以时间顺序累积并存储多个输入信号作为历史值的历史存储器。它还包括一个输出模块，用于当内部状态超过预定阈值时输出输出信号，内部状态基于多个输入信号的乘积和相应的耦合系数之和。历史价值取决于内部状态的变化。神经网络元件被配置为在输出模块触发之后立即从内部状态减去预定值，并且在输出模块触发之后根据历史值执行用于加强或衰减耦合系数的学习。

5. 发明申请

US20090206477A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20090206477A1
公开(公告)日：2009-08-20
申请号：US12369490
申请日：2009-02-11
申请人： Takanori MAEBASHI , Nobuaki Miyakawa
发明人： Takanori MAEBASHI , Nobuaki Miyakawa
IPC分类号： H01L23/498 , H01L21/98
CPC分类号： H01L24/12 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L23/5389 , H01L24/14 , H01L24/16 , H01L24/81 , H01L24/90 , H01L25/50 , H01L2221/68372 , H01L2224/0401 , H01L2224/06102 , H01L2224/13009 , H01L2224/13099 , H01L2224/1403 , H01L2224/14051 , H01L2224/2518 , H01L2224/81136 , H01L2224/81801 , H01L2224/83136 , H01L2225/06513 , H01L2225/06541 , H01L2225/06575 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/01074 , H01L2924/01078 , H01L2924/01088 , H01L2924/04941 , H01L2924/07802 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00
摘要： A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer comprises an lamination surface to which another wafer is laminated; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another surface so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit and is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion so as to protrude from the lamination surface with a height equal to or larger than that of the protruding connection portion.
摘要翻译：半导体器件具有彼此层叠的多个晶片，其中：每个晶片包括层叠另一晶片的层叠表面; 所述层叠面具有与所述另一表面电连接以形成半导体电路的电信号连接部; 彼此面对的电信号连接部中的至少一个是从层叠面突出的突出连接部，以及与半导体电路绝缘的加强突出部，并且设置在突出连接部未设置在形成有突出连接部的层叠面上的区域中，以从层叠面突出的高度等于或等于大于突出连接部分的尺寸。

6. 发明授权

US07370328B2 Method for assigning job in parallel processing method and parallel processing method 失效
标题翻译：并行处理方法和并行处理方法分配作业的方法
公开(公告)号：US07370328B2
公开(公告)日：2008-05-06
申请号：US10257913
申请日：2002-04-25
申请人： Sou Yamada , Shinjiro Inabata , Nobuaki Miyakawa , Hajime Takashima , Kunihiro Kitamura , Unpei Nagashima
发明人： Sou Yamada , Shinjiro Inabata , Nobuaki Miyakawa , Hajime Takashima , Kunihiro Kitamura , Unpei Nagashima
IPC分类号： G06F9/44 , G06F15/16 , G06F15/163
CPC分类号： G06F9/5066 , G06F9/4881
摘要： When parallel processing is executed by parallel computers composed of a host computer and a plurality of processors connected to the host computer through a common bus, there is provided a method of assigning jobs to respective processors with high efficiency. A job in which a ratio between a communication time and a calculation time is larger than a predetermined value or larger than a fraction of processors and a job in which a ratio between a communication time and a calculation time is smaller than a predetermined value or smaller than a fraction of processors can be alternately assigned to respective processors. Alternatively, jobs are assigned to respective processors in such a manner that a plurality of processors and a plurality of jobs are divided into a plurality of groups in a one-to-one relation, jobs in which sizes comprising communication time and calculation time and ratios between the communication times and the calculation times approximate to each other may belong to different job groups and the order in which the jobs in which the sizes comprising the communication time and the calculation time and the ratios between the communication times and the calculation times approximate to each other are assigned within respective job groups may differ from each other among a plurality of job groups.
摘要翻译：当并行处理由主计算机和通过公共总线连接到主计算机的多个处理器组成的并行计算机执行时，提供了一种以高效率将作业分配给各个处理器的方法。其中通信时间和计算时间之间的比率大于预定值或大于处理器的一部分的工作，以及通信时间和计算时间之间的比率小于预定值或更小的作业可以将一小部分处理器交替分配给相应的处理器。或者，将作业分配给各个处理器，使得多个处理器和多个作业以一对一的关系被分成多个组，其中包括通信时间和计算时间和比率的尺寸的作业在通信时间和彼此近似的计算时间之间可以属于不同的作业组，并且其中包括通信时间和计算时间的尺寸以及通信时间与计算时间之间的比率近似于彼此分配在各个作业组中可以在多个作业组中彼此不同。

7. 发明申请

US20060021706A1 Adhesive injection apparatus and method 有权
标题翻译：粘合剂注射装置和方法
公开(公告)号：US20060021706A1
公开(公告)日：2006-02-02
申请号：US11193368
申请日：2005-08-01
申请人： Nobuaki Miyakawa , Hiroyuki Toshima , Natsuo Nakamura , Takahiro Kimura
发明人： Nobuaki Miyakawa , Hiroyuki Toshima , Natsuo Nakamura , Takahiro Kimura
IPC分类号： B32B37/00
CPC分类号： H01L21/67092 , H01L21/6715 , H01L2924/0002 , H01L2924/00
摘要： Adhesive injection apparatus, designed to inject an adhesive into gaps between a plurality of layers of flat plate members, includes: a receptacle for holding therein the flat plate members; an evacuation section for evacuating the interior of the receptacle and the gaps between the flat plate members; an adhesive supply section for supplying the adhesive into the receptacle; and a gas introduction section for introducing a gas into the receptacle to produce a pressure difference between the interior of the receptacle and the gaps between the flat plate members, so as to allow the adhesive to be injected from all around the flat plate members into the gaps.
摘要翻译：粘合剂注射装置，设计用于将粘合剂注入到多个平板构件层之间的间隙中，包括：用于在其中保持平板构件的容器; 用于抽出容器内部和平板构件之间的间隙的抽空部; 用于将粘合剂供应到容器中的粘合剂供应部分; 以及用于将气体引入容器中以在容器内部和平板构件之间的间隙之间产生压力差的气体引入部分，以便允许粘合剂从平板构件的周围注入到差距

8. 发明授权

US06799151B1 Method and apparatus for parallel processing 失效
标题翻译：并行处理方法和装置
公开(公告)号：US06799151B1
公开(公告)日：2004-09-28
申请号：US09544201
申请日：2000-04-07
申请人： So Yamada , Shinjiro Inabata , Nobuaki Miyakawa , Hajime Takashima , Kunihiro Kitamura , Shigeru Obara
发明人： So Yamada , Shinjiro Inabata , Nobuaki Miyakawa , Hajime Takashima , Kunihiro Kitamura , Shigeru Obara
IPC分类号： G06F1750
CPC分类号： G06F9/5066 , G06F8/45 , G06F17/10
摘要： Matrix element calculation carried out efficiently without the overhead of communication between a host computer and processor elements even in parallel calculation utilizing a low-cost communication device and multiple processor elements having memories of a small capacity. In a method for calculating molecular orbitals, for example, all elements F(I, J) of a Fock matrix are calculated where an outermost loop is a loop associated with combinations (RT) of contracted shell R and contracted shell T which satisfy relationships R≦Nshell and T≦R. A second loop is a loop associated with contracted shell S, and a third loop is a loop associated with contracted shell U. Alternatively, the second loop is a loop associated with the contracted shell U, and the third loop is a loop associated with the contracted shell S. The value of S ranges from 1 to R, and the value of U ranges from 1 to R. Calculation of predetermined electron repulsion integrals and calculation of a predetermined part of Fock matrix elements utilizing the result of the calculation is carried out inside the third loop.
摘要翻译：即使在使用低成本通信装置的并行计算和具有小容量的存储器的多个处理器元件的情况下，也可以有效地进行矩阵元素计算，而无需主计算机和处理器元件之间的通信开销。在用于计算分子轨道的方法中，例如，计算Fock矩阵的所有元素F（I，J），其中最外面的循环是与收缩壳体R和收缩壳体T的组合（RT）相关联的回路，其满足关系R <= Nshell和T <= R。第二个循环是与收缩壳体S相关联的循环，第三个循环是与收缩的壳体U相关联的循环。或者，第二个循环是与收缩的壳体U相关联的循环，第三个循环是与 S的值范围从1到R，U的值在1到R之间。使用计算结果计算预定的电子斥力积分和计算预定部分的Fock矩阵元素在第三个循环内。

9. 发明授权

US5572447A Coordinate difference calculating device 失效
标题翻译：坐标差计算装置
公开(公告)号：US5572447A
公开(公告)日：1996-11-05
申请号：US160800
申请日：1993-12-03
申请人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
发明人： Shinjiro Toyoda , Hitoshi Ikeda , Eiri Hashimoto , Nobuaki Miyakawa
IPC分类号： G06F7/544 , G06F17/50 , G01N15/02 , G01B21/16
CPC分类号： G06F7/544 , G06F19/704 , G06F19/701
摘要： A device for calculating differences includes a difference circuit for generating difference signals .DELTA.x.sub.j =x.sub.j -x.sub.i, .DELTA.y.sub.j =y.sub.j -y.sub.i, and .DELTA.z.sub.j =z.sub.j -z.sub.i between coordinates of i having (x.sub.i, y.sub.i, z.sub.i) coordinate signals and coordinates of j having (x.sub.j, y.sub.j, z.sub.j) coordinate signals in an orthogonal coordinate system. The difference circuit includes an x-axis circuit, responsive to the x.sub.i and x.sub.j signals having a first circuit for receiving the x.sub.i coordinate signal and the x.sub.j coordinate signal and generating the .DELTA.x.sub.j ; a comparison circuit for comparing the x.sub.i and x.sub.j signals and determining whether the .DELTA.x.sub.j is less than a first set value -L.sub.x /2 corresponding to a length of a side of a virtual rectangular parallelepiped or greater than a second set value L.sub.x /2 corresponding to the length of the side of the virtual rectangular parallelepiped, L.sub.x being a value indicating the length of an elongated side in the x-axis direction of the virtual rectangular parallelepiped; an adder circuit for receiving the L.sub.x and .DELTA.x.sub.j and adding the L.sub.x to .DELTA.x.sub.j when .DELTA.x.sub.j is less than -L.sub.x /2; and a subtraction circuit for receiving the L.sub.x and .DELTA.x.sub.j and subtracting L.sub.x from .DELTA.x.sub.j when .DELTA.x.sub.j is greater than L.sub.x /2. The difference circuit includes y-axis and z-axis circuits similar to the x-axis circuit.
摘要翻译：用于计算差分的装置包括用于产生具有（xi，yi，zi）坐标信号和坐标的坐标之间的差分信号DELTA xj = xj-xi，DELTA yj = yj-yi和DELTA zj = zj-zi的差分电路具有在正交坐标系中的（xj，yj，zj）坐标信号的j。差分电路包括x轴电路，响应于具有用于接收xi坐标信号和xj坐标信号并产生DELTA xj的第一电路的xi和xj信号; 用于比较xi和xj信号并确定DELTA xj是否小于对应于虚拟长方体的一侧的长度或大于第二设定值Lx / 2的对应的第一设定值-Lx / 2的比较电路到虚拟长方体的一侧的长度，Lx是表示虚拟长方体的x轴方向上的细长侧的长度的值; 加法器电路，用于当DELTA xj小于-Lx / 2时，接收Lx和DELTA xj并将Lx加到DELTA xj; 以及减法电路，用于当DELTA xj大于Lx / 2时，从DELTA xj接收Lx和DELTA xj并从DELTA xj中减去Lx。差分电路包括类似于x轴电路的y轴和z轴电路。

10. 发明授权

US4578693A Semiconductive photodetector device 失效
标题翻译：半导体光电探测器
公开(公告)号：US4578693A
公开(公告)日：1986-03-25
申请号：US505447
申请日：1983-06-17
申请人： Yoshiaki Yazawa , Nobuaki Miyakawa , Toji Mukai , Takahide Ikeda , Tatsuya Kamei
发明人： Yoshiaki Yazawa , Nobuaki Miyakawa , Toji Mukai , Takahide Ikeda , Tatsuya Kamei
IPC分类号： H01L27/146 , H01L31/0216 , H01L31/10 , H01L27/14 , H01L31/00
CPC分类号： H01L27/14643 , H01L31/02164
摘要： In a semiconductive photodetector device having a semiconductor substrate and a plurality of photodiodes juxtaposed in one major surface of the semiconductor substrate, exposed edges of adjacent pn junctions of adjacent photodiodes are covered with a polysilicon film.
摘要翻译：在具有半导体衬底和并置在半导体衬底的一个主表面上的多个光电二极管的半导体光电检测器件中，相邻光电二极管的相邻pn结的暴露边缘被多晶硅膜覆盖。

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