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1. 发明授权

US08048763B2 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US08048763B2
公开(公告)日：2011-11-01
申请号：US12718047
申请日：2010-03-05
申请人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
发明人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
IPC分类号： H01L21/76
CPC分类号： H01L25/117 , H01L21/6835 , H01L21/76898 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/81139 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/01019 , H01L2924/01037 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.
摘要翻译：在衬底上形成有从衬底的主表面延伸到所需深度的深度隔离沟槽，其中埋置有绝缘膜以形成通过隔离部分。随后，在衬底的主表面上形成MOSFET之后，在衬底的主表面上沉积层间绝缘膜。然后，在由直通隔离部包围的区域中形成从层间绝缘膜的上表面延伸到衬底厚度内的深度的深导电沟槽。随后，将导电膜埋在深导电沟槽中以形成通过互连部分。然后，在将基板的下表面研磨抛光至不暴露通过隔离部分和通过互连部分的程度之后，进行湿法蚀刻，使其暴露于每个通过隔离部分的下部的部分，以及直通互连部分。

2. 发明授权

US07986045B2 Semiconductor device having an increased area of one of the opposing electrode parts for preventing generation of unconnected positions the electrodes on the bonded wafers 有权
标题翻译：半导体器件具有增加的一个相对电极部分的面积，用于防止在接合晶片上产生不连接位置的电极
公开(公告)号：US07986045B2
公开(公告)日：2011-07-26
申请号：US12194672
申请日：2008-08-20
申请人： Takanori Maebashi , Nobuaki Miyakawa
发明人： Takanori Maebashi , Nobuaki Miyakawa
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/16 , H01L21/563 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/12 , H01L24/17 , H01L24/83 , H01L24/90 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/05001 , H01L2224/05022 , H01L2224/05085 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/05572 , H01L2224/05684 , H01L2224/13078 , H01L2224/13099 , H01L2224/131 , H01L2224/171 , H01L2224/838 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01088 , H01L2924/04941 , H01L2924/07802 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2924/00014
摘要： In this semiconductor device, connection parts between wafers are electrically insulated from each other, and a junction face shape of second electrical signal connection parts is larger than the shape of a positioning margin face that is formed by an outer shape when the periphery of a minimum junction face, which has half the area of a junction area of the first electrical signal connection part, is enclosed by a same width dimension as a positioning margin dimension between the first wafer and the second wafer.
摘要翻译：在该半导体装置中，晶片之间的连接部分彼此电绝缘，并且第二电信号连接部分的接合面形状大于当外部形状为最小的周边形成的定位边缘面的形状时具有第一电信号连接部分的接合区域的一半面积的接合面被与第一晶片和第二晶片之间的定位边界尺寸相同的宽度尺寸包围。

3. 发明授权

US07948088B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07948088B2
公开(公告)日：2011-05-24
申请号：US12063606
申请日：2006-08-25
申请人： Toshio Saito , Satoshi Moriya , Morio Nakamura , Goichi Yokoyama , Tatsuyuki Saito , Nobuaki Miyakawa
发明人： Toshio Saito , Satoshi Moriya , Morio Nakamura , Goichi Yokoyama , Tatsuyuki Saito , Nobuaki Miyakawa
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L21/763 , H01L21/76898 , H01L21/823871 , H01L21/823878 , H01L23/3128 , H01L23/481 , H01L24/45 , H01L24/48 , H01L25/50 , H01L27/0203 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.
摘要翻译：为了提高具有多个芯片彼此堆叠并附接的三维结构的半导体器件的制造成品，形成在每个芯片（C2）中的每个导电槽（4A）的开口形状获得从晶片（W2）的长方形的长方形的导体槽（4A）的长度方向的长度方向的数量和长边方向的X方向的导体槽的数量使整个晶片（W2）的Y方向大致相等，由此导电膜嵌入导电槽内的膜应力减小，剥离和微裂纹的产生导致膜或翘曲和晶片（W2）的裂纹被阻止。

4. 发明授权

US07795137B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07795137B2
公开(公告)日：2010-09-14
申请号：US12063718
申请日：2006-08-25
申请人： Toshio Saito , Akira Otaguro , Manabu Otake , Yoshiya Takahira , Namio Katagiri , Nobuaki Miyakawa
发明人： Toshio Saito , Akira Otaguro , Manabu Otake , Yoshiya Takahira , Namio Katagiri , Nobuaki Miyakawa
IPC分类号： H01L21/4763
CPC分类号： H01L25/50 , H01L21/76898 , H01L21/823871 , H01L23/481 , H01L23/585 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L27/0694 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： When a tungsten film (43) is embedded inside of a conductive groove (4A) formed in a wafer (W2) and a silicon oxide film (36) thereon and having a high aspect ratio, film formation and etch back of the tungsten film (43) are successively performed in a chamber of the same apparatus, therefore, a film thickness of the tungsten film (43) deposited in one film formation step is made to be thin. Whereby problems, such as exfoliation of the tungsten film (43), generation of micro-cracks, and occurrence of warpage and cracks of the wafer (W2), are avoided.
摘要翻译：当将钨膜（43）嵌入形成在晶片（W2）和氧化硅膜（36）上的导电槽（4A）内并具有高纵横比，钨膜的成膜和回蚀（ 43）在相同装置的腔室中连续地进行，因此，在一个成膜步骤中沉积的钨膜（43）的膜厚变薄。由此，避免了钨膜（43）的剥离，微裂纹的产生，以及晶片（W2）的翘曲和裂纹的发生等问题。

5. 发明申请

US20100167495A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND WAFER 有权
公开(公告)号：US20100167495A1
公开(公告)日：2010-07-01
申请号：US12718047
申请日：2010-03-05
申请人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
发明人： Nobuaki Miyakawa , Takanori Maebashi , Takahiro Kimura
IPC分类号： H01L21/762
CPC分类号： H01L25/117 , H01L21/6835 , H01L21/76898 , H01L21/823475 , H01L21/823481 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2224/16145 , H01L2224/81139 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06582 , H01L2924/01019 , H01L2924/01037 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
摘要： A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

6. 发明申请

US20090057890A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090057890A1
公开(公告)日：2009-03-05
申请号：US12194672
申请日：2008-08-20
申请人： Takanori MAEBASHI , Nobuaki Miyakawa
发明人： Takanori MAEBASHI , Nobuaki Miyakawa
IPC分类号： H01L23/48
CPC分类号： H01L24/16 , H01L21/563 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/12 , H01L24/17 , H01L24/83 , H01L24/90 , H01L25/0657 , H01L25/50 , H01L2221/68372 , H01L2224/05001 , H01L2224/05022 , H01L2224/05085 , H01L2224/05124 , H01L2224/05147 , H01L2224/05184 , H01L2224/05572 , H01L2224/05684 , H01L2224/13078 , H01L2224/13099 , H01L2224/131 , H01L2224/171 , H01L2224/838 , H01L2225/06513 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01088 , H01L2924/04941 , H01L2924/07802 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2924/00014
摘要： In this semiconductor device, connection parts between wafers are electrically insulated from each other, and a junction face shape of second electrical signal connection parts is larger than the shape of a positioning margin face that is formed by an outer shape when the periphery of a minimum junction face, which has half the area of a junction area of the first electrical signal connection part, is enclosed by a same width dimension as a positioning margin dimension between the first wafer and the second wafer.
摘要翻译：在该半导体装置中，晶片之间的连接部分彼此电绝缘，并且第二电信号连接部分的接合面形状大于当外部形状为最小的周边形成的定位边缘面的形状时具有第一电信号连接部分的接合区域的一半面积的接合面被与第一晶片和第二晶片之间的定位边界尺寸相同的宽度尺寸包围。

7. 发明授权

US06631391B1 Parallel computer system and parallel computing method 失效
标题翻译：并行计算机系统和并行计算方法
公开(公告)号：US06631391B1
公开(公告)日：2003-10-07
申请号：US09544359
申请日：2000-04-06
申请人： Shinjiro Inabata , So Yamada , Nobuaki Miyakawa , Takashi Amisaki , Hajime Takashima , Kunihiro Kitamura
发明人： Shinjiro Inabata , So Yamada , Nobuaki Miyakawa , Takashi Amisaki , Hajime Takashima , Kunihiro Kitamura
IPC分类号： G06F738
CPC分类号： G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30025 , G06F9/3885
摘要： There is provided a parallel computer and a parallel computing method which allows high precision parallel calculation to be executed without requiring a hardware scale while maintaining high calculation speed. A system is constructed by connecting a host processor with a plurality of special purpose processors via buses. The host processor carries out the operation in a format of double-precision floating-point and the special purpose processor carries out the operation in an internal format of floating-point. The special purpose processor comprises an input data converting section for converting from the double-precision to the internal format and an output data converting section for converting from the internal format to the double-precision. Because the sign part and the exponent part can use data in common in the data before and after the conversion, only the mantissa part is converted by a specific procedure.
摘要翻译：提供了并行计算机和并行计算方法，其允许执行高精度并行计算，而不需要硬件规模，同时保持高的计算速度。通过总线将主机处理器与多个专用处理器连接构成系统。主机处理器以双精度浮点格式进行操作，专用处理器以浮点的内部格式进行操作。专用处理器包括用于从双精度转换为内部格式的输入数据转换部分和用于从内部格式转换为双精度的输出数据转换部分。因为符号部分和指数部分可以在转换之前和之后的数据中使用共同的数据，所以仅通过特定过程转换尾数部分。

8. 发明授权

US6073155A Floating-point accumulator 失效
标题翻译：浮点累加器
公开(公告)号：US6073155A
公开(公告)日：2000-06-06
申请号：US901671
申请日：1997-07-28
申请人： Shinjiro Inabata , So Yamada , Shinjiro Toyoda , Nobuaki Miyakawa
发明人： Shinjiro Inabata , So Yamada , Shinjiro Toyoda , Nobuaki Miyakawa
IPC分类号： G06F7/485 , G06F7/50 , G06F17/10 , G06F7/38
CPC分类号： G06F7/485
摘要： To obtain the sufficiently precise result of floating-point accumulation even if the quantity of computation is enormous, a floating-point accumulator according to the present invention is constituted as follows:When two floating-point data are stored in any of shift registers, the two data are respectively output to BUS0 and BUS1 via one connected to the shift register of buffers. The two output data are input to an adder via BUS0 and BUS1 and output as added result data after adding the floating-point numbers. The above added result data is returned to each input of the shift registers via BUSW and a multiplexer and written into the shift register corresponding to the addition of the higher level by one of the shift register holding floating-point data before addition. The floating-point numbers are accumulated by repeating the above operation.
摘要翻译：为了获得足够精确的浮点积累结果，即使计算量很大，根据本发明的浮点累加器如下构成：当两个浮点数据存储在任何移位寄存器中时，两个数据分别通过连接到缓冲器移位寄存器的一个BUS0和BUS1输出。两个输出数据通过BUS0和BUS1输入加法器，并在添加浮点数后作为相加结果数据输出。上述相加的结果数据通过BUSW和多路复用器返回到移位寄存器的每个输入，并且在相加之前通过移位寄存器保持浮点数据之一来写入与移位寄存器相对应的移位寄存器。通过重复上述操作来累积浮点数。

9. 发明授权

US5204838A High speed readout circuit 失效
标题翻译：高速读出电路
公开(公告)号：US5204838A
公开(公告)日：1993-04-20
申请号：US751618
申请日：1991-08-21
申请人： Jinshu Son , Nobuaki Miyakawa
发明人： Jinshu Son , Nobuaki Miyakawa
IPC分类号： G11C7/06 , G11C16/26 , H03K5/02 , H03K5/24
CPC分类号： G11C16/26 , G11C7/06 , G11C7/067 , H03K5/023 , H03K5/249
摘要： The high speed readout circuit has an amplifier unit and an operating point setting unit and reads data from a memory sense line at high speed. The circuit further includes a unit for setting an operating point of the amplifier unit by short-circuiting the input and output terminals of the amplifier in response to a first control signal and precharging the sense line up to the operating point, and a unit for setting the sense line at a voltage slightly deviating the operating point in response to a second control signal by making use of a Miller capacitance and sensing the variations from the preset voltage during a reading process.
摘要翻译：高速读出电路具有放大器单元和工作点设定单元，并以高速从存储感测线读出数据。该电路还包括一个单元，用于根据第一控制信号短路放大器的输入和输出端，并将感测线预充电到工作点来设置放大器单元的工作点，以及一个设置单元通过利用米勒电容并在读取过程中感测来自预设电压的变化，响应于第二控制信号使电压稍微偏离工作点的感测线。

10. 发明授权

US5050127A Memory device with improved common data line bias arrangement 失效
标题翻译：具有改进的公共数据线偏置布置的存储器件
公开(公告)号：US5050127A
公开(公告)日：1991-09-17
申请号：US423947
申请日：1989-10-19
申请人： Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
发明人： Kinya Mitsumoto , Shinji Nakazato , Yoshiaki Yazawa , Masanori Odaka , Hideaki Uchida , Nobuaki Miyakawa
IPC分类号： G11C11/417 , G11C7/10
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051
摘要： A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

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