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1. 发明授权

US06252294B1 Semiconductor device and semiconductor storage device 失效
标题翻译：半导体器件和半导体存储器件
公开(公告)号：US06252294B1
公开(公告)日：2001-06-26
申请号：US09438578
申请日：1999-11-12
申请人： Nobuyoshi Hattori , Hideki Naruoka , Hidekazu Yamamoto
发明人： Nobuyoshi Hattori , Hideki Naruoka , Hidekazu Yamamoto
IPC分类号： H01L2701
CPC分类号： H01L21/84 , H01L23/26 , H01L27/1203 , H01L2924/0002 , Y10S257/903 , Y10S257/913 , H01L2924/00
摘要： A semiconductor device and a semiconductor storage device having an SOI structure and being enable sufficient gettering performance without imposing limitations on the freedom of design of an LSI circuit. A semiconductor device includes a semiconductor wafer of SOI structure which has a insulation layer and a silicon layer provided thereon, wherein the semiconductor wafer includes a plurality of element fabrication regions where semiconductor elements are fabricated, and a cutting region provided between the element fabrication regions. Gettering sites are formed in the cutting region by means of embedding a gettering member into grooves of predetermined depth.
摘要翻译：具有SOI结构的半导体器件和半导体存储器件，并且能够实现充分的吸杂性能，而不会对LSI电路的设计自由度施加限制。半导体器件包括SOI结构的半导体晶片，其具有绝缘层和设置在其上的硅层，其中半导体晶片包括多个制造半导体元件的元件制造区域和设置在元件制造区域之间的切割区域。通过将吸气构件嵌入到预定深度的凹槽中，在切割区域中形成吸气部位。

2. 发明授权

US06844242B2 Method of manufacturing SOI wafer 失效
标题翻译：制造SOI晶圆的方法
公开(公告)号：US06844242B2
公开(公告)日：2005-01-18
申请号：US10113291
申请日：2002-04-02
申请人： Hideki Naruoka , Nobuyoshi Hattori , Hidekazu Yamamoto
发明人： Hideki Naruoka , Nobuyoshi Hattori , Hidekazu Yamamoto
IPC分类号： H01L21/683 , H01L21/00 , H01L21/02 , H01L21/762 , H01L27/12 , H01L21/30 , H01L21/46
CPC分类号： H01L21/67092 , H01L21/76251 , Y10S414/138
摘要： A boat (4) has a recess (5) for supporting a laminated wafer (50). The recess (5) has a first side surface (5a), a first bottom surface (5b), a second side surface (5c), a second bottom surface (5d) and a third side surface (5e). Viewing from an upper surface of the boat (4), the second bottom surface (5d) is located in a position lower than the first bottom surface (5b). The laminated wafer (50) is mounted on the boat (4) in the state that a side surface of a first silicon wafer (1) is not in contact with the second bottom surface (5d) of the recess (5) and a side surface of a second silicon wafer (2) is in contact with the first bottom surface (5b) of the recess (5). A second main surface (2a) of the second silicon wafer (2) is in contact with the first side surface (5a) of the recess (5) and a second main surface (1a) of the first silicon wafer (1) is in contact with the third side surface (5e) of the recess (5).
摘要翻译：船（4）具有用于支撑层叠晶片（50）的凹部（5）。凹部（5）具有第一侧面（5a），第一底面（5b），第二侧面（5c），第二底面（5d）和第三侧面（5e）。从船（4）的上表面看，第二底面（5d）位于比第一底面（5b）低的位置。在第一硅晶片（1）的侧面与凹部（5）的第二底面（5d）不接触的状态下，将层叠晶片（50）安装在舟皿（4）上，第二硅晶片（2）的表面与凹部（5）的第一底表面（5b）接触。第二硅晶片（2）的第二主表面（2a）与凹部（5）的第一侧表面（5a）接触，并且第一硅晶片（1）的第二主表面（1a）处于与凹部（5）的第三侧表面（5e）接触。

3. 发明授权

US06914307B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06914307B2
公开(公告)日：2005-07-05
申请号：US10657068
申请日：2003-09-09
申请人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
发明人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
IPC分类号： H01L21/76 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/12 , H01L29/45 , H01L29/786 , H01L29/76
CPC分类号： H01L21/76286 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/458
摘要： A semiconductor device includes a semiconductor layer, a plurality of semiconductor elements formed on the semiconductor layer, and an isolation film provided in a surface of the semiconductor layer, semiconductor elements being electrically isolated from each other by the isolation film. The semiconductor device also includes a PN junction portion provided under the isolation film and formed by two semiconductor regions of different conductivity types in the semiconductor layer. The isolation film includes a nitride film provided in a position corresponding to a top of the PN junction portion and has a substantially uniform thickness across the two semiconductor regions and an upper oxide film and a lower oxide film which are provided in upper and lower portions of the nitride film. The surface of the semiconductor layer is silicidized in such a state that a surface of the isolation film is exposed.
摘要翻译：半导体器件包括半导体层，形成在半导体层上的多个半导体元件和设置在半导体层的表面中的隔离膜，半导体元件通过隔离膜彼此电隔离。半导体器件还包括设置在隔离膜下方并由半导体层中由不同导电类型的两个半导体区域形成的PN结部分。隔离膜包括设置在与PN结部分的顶部相对应的位置的氮化物膜，并且在两个半导体区域上具有基本上均匀的厚度，以及设置在上部和下部的上部氧化物膜和低级氧化物膜氮化膜。半导体层的表面在隔离膜的表面露出的状态下被硅化。

4. 发明授权

US06646306B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06646306B2
公开(公告)日：2003-11-11
申请号：US09985020
申请日：2001-11-01
申请人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
发明人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
IPC分类号： H01L2701
CPC分类号： H01L21/76286 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/458
摘要： A semiconductor device that prevents metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film, a polysilicon film selectively provided on the trench isolation oxide film, a silicon layer provided on the polysilicon film, and a side wall spacer provided on a side surface of the polysilicon film. The polysilicon film is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region and an N-type well region in a SOI layer across the two well regions.
摘要翻译：一种防止金属污染的半导体器件以及半导体器件的制造方法。区域（NR）和区域（PR）由沟槽隔离氧化膜，选择性地设置在沟槽隔离氧化膜上的多晶硅膜，设置在多晶硅膜上的硅层和设置在侧面上的侧壁隔离物多晶硅膜的表面。多晶硅膜设置在对应于跨越两个阱区域的SOI层中的P型阱区域和N型阱区域的PN结部分JP的顶部的位置。

5. 发明申请

US20050212056A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050212056A1
公开(公告)日：2005-09-29
申请号：US11135522
申请日：2005-05-24
申请人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
发明人： Toshiaki Iwamatsu , Takashi Ipposhi , Hideki Naruoka , Nobuyoshi Hattori , Shigeto Maegawa , Yasuo Yamaguchi , Takuji Matsumoto
IPC分类号： H01L21/76 , H01L21/762 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/12 , H01L29/45 , H01L29/786
CPC分类号： H01L21/76286 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/458
摘要： To provide a semiconductor device capable of preventing drawbacks from being caused by metal pollution and a method of manufacturing the semiconductor device. A region (NR) and a region (PR) are defined by a trench isolation oxide film (ST21), a polysilicon film (PS21) is selectively provided on the trench isolation oxide film (ST21), a silicon layer (S22) is provided on the polysilicon film (PS21), and a side wall spacer (SW2) is provided on a side surface of the polysilicon film (PS21). The polysilicon film (PS21) is provided in a position corresponding to a top of a PN junction portion JP of a P-type well region (WR11) and an N-type well region (WR12) in an SOI layer 3 across the two well regions.
摘要翻译：提供能够防止金属污染引起的缺陷的半导体器件以及半导体器件的制造方法。区域（NR）和区域（PR）由沟槽隔离氧化膜（ST21）限定，在沟槽隔离氧化膜（ST21）上选择性地设置多晶硅膜（PS21），硅层（S 22）设置在多晶硅膜（PS21）上，在多晶硅膜（PS21）的侧面设置有侧壁隔板（SW2）。多晶硅膜（PS21）被设置在对应于SOI层3中的P型阱区域（WR 11）和N型阱区域（WR 12）的PN结部分JP的顶部的位置两个井区。

6. 发明授权

US06232201B1 Semiconductor substrate processing method 失效
标题翻译：半导体衬底处理方法
公开(公告)号：US06232201B1
公开(公告)日：2001-05-15
申请号：US09113155
申请日：1998-07-10
申请人： Yoshiko Yoshida , Hideki Naruoka , Yasuhiro Kimura , Yasuo Yamaguchi , Toshiaki Iwamatsu , Yuuichi Hirano
发明人： Yoshiko Yoshida , Hideki Naruoka , Yasuhiro Kimura , Yasuo Yamaguchi , Toshiaki Iwamatsu , Yuuichi Hirano
IPC分类号： H01L2176
CPC分类号： H01L21/7624 , H01L21/3105 , H01L21/31155
摘要： An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.
摘要翻译：目的在于提供一种半导体衬底处理方法以及防止从衬底的边缘部分形成微粒的半导体衬底。在SOI衬底（10）的半径方向上将硅离子注入到SOI衬底（10）的边缘部分中，以使SOI衬底（10）的边缘部分中的掩埋氧化膜（2）成为硅丰富的状态。因此，提供SOI衬底（100），其中掩埋氧化膜（2）在边缘部分中基本上被去除。

7. 发明授权

US06563172B2 Semiconductor substrate processing method 失效
公开(公告)号：US06563172B2
公开(公告)日：2003-05-13
申请号：US09770388
申请日：2001-01-29
申请人： Yoshiko Yoshida , Hideki Naruoka , Yasuhiro Kimura , Yasuo Yamaguchi , Toshiaki Iwamatsu , Yuuichi Hirano
发明人： Yoshiko Yoshida , Hideki Naruoka , Yasuhiro Kimura , Yasuo Yamaguchi , Toshiaki Iwamatsu , Yuuichi Hirano
IPC分类号： H01L2701
CPC分类号： H01L21/7624 , H01L21/3105 , H01L21/31155
摘要： An object is to provide a semiconductor substrate processing method and a semiconductor substrate that prevent formation of particles from the edge part of the substrate. Silicon ions are implanted into the edge part of an SOI substrate (10) in the direction of radiuses of the SOI substrate (10) to bring a buried oxide film (2) in the edge part of the SOI substrate (10) into a silicon-rich state. Thus an SOI substrate (100) is provided, where the buried oxide film (2) has substantially been eliminated in the edge part.

8. 发明授权

US09211626B2 Semiconductor device and grinding method of semiconductor device 有权
标题翻译：半导体器件的半导体器件和研磨方法
公开(公告)号：US09211626B2
公开(公告)日：2015-12-15
申请号：US14252130
申请日：2014-04-14
申请人： Takeshi Kondo , Hideki Naruoka , Hajime Tsukahara
发明人： Takeshi Kondo , Hideki Naruoka , Hajime Tsukahara
IPC分类号： H01L23/36 , B24B7/22 , H01L23/00 , H01L23/433 , H01L23/488 , B24B37/013 , B24B37/04
CPC分类号： B24B7/228 , B24B37/013 , B24B37/042 , H01L23/4334 , H01L23/488 , H01L24/33 , H01L2224/48091 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： A semiconductor device includes a semiconductor chip, and a grinding-processed layer laminated on one surface of the semiconductor chip. Further, the semiconductor device includes a sealing resin that seals the semiconductor chip and the grinding-processed layer; and a metal remaining-thickness checking portion provided adjacent to the grinding-processed layer, sealed by the sealing resin, and having a inclined plane that is inclined with respect to a laminating direction of the grinding-processed layer.
摘要翻译：半导体器件包括半导体芯片和层叠在半导体芯片的一个表面上的研磨处理层。此外，半导体器件包括密封半导体芯片和研磨处理层的密封树脂; 以及与所述研磨处理层相邻设置的密封树脂密封的金属剩余厚度检查部，具有相对于所述研磨处理层的层叠方向倾斜的倾斜面。

9. 发明申请

US20050208322A1 Method for treating substrates for microelectronics and substrates obtained by said method 有权
标题翻译：用于处理通过所述方法获得的用于微电子学和衬底的衬底的方法
公开(公告)号：US20050208322A1
公开(公告)日：2005-09-22
申请号：US11063867
申请日：2005-02-24
申请人： Thierry Barge , Bruno Ghyselen , Toshiaki Iwamatsu , Hideki Naruoka , Junichiro Furihata , Kiyoshi Mitani
发明人： Thierry Barge , Bruno Ghyselen , Toshiaki Iwamatsu , Hideki Naruoka , Junichiro Furihata , Kiyoshi Mitani
IPC分类号： H01L21/306 , H01L21/762 , G03C5/00 , H01L21/00 , H01L21/30 , H01L21/46 , H01L21/84 , H01L29/06 , H01L29/12 , H01L29/30
CPC分类号： H01L21/306 , H01L21/30625 , H01L21/76254 , Y10T428/12528
摘要： An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.
摘要翻译：根据本发明的多层晶片的实施例包括基底基板，与基底基板相关联的第一层，以及在轴向方向上与基底基板相反一侧的第一层上的第二层，并且具有侧向边缘。第一层包括沿着垂直于轴向方向测量的沿轴向突出并且横向邻近第二层布置的脊，用于保护侧边缘。该脊可以围绕横向边缘围绕轴向横截面以防止边缘下降。此外，脊可以具有大于第二层的轴向厚度的轴向高度。在一个实施例中，第二层包括氧化半导体，第一层包括氧化绝缘体。

10. 发明申请

US20140319671A1 SEMICONDUCTOR DEVICE AND GRINDING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和研磨方法
公开(公告)号：US20140319671A1
公开(公告)日：2014-10-30
申请号：US14252130
申请日：2014-04-14
申请人： Takeshi Kondo , Hideki Naruoka , Hajime Tsukahara
发明人： Takeshi Kondo , Hideki Naruoka , Hajime Tsukahara
IPC分类号： H01L21/304 , H01L23/367 , B24B7/22
CPC分类号： B24B7/228 , B24B37/013 , B24B37/042 , H01L23/4334 , H01L23/488 , H01L24/33 , H01L2224/48091 , H01L2224/48247 , H01L2224/73215 , H01L2224/73265 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： A semiconductor device includes a semiconductor chip, and a grinding-processed layer laminated on one surface of the semiconductor chip. Further, the semiconductor device includes a sealing resin that seals the semiconductor chip and the grinding-processed layer; and a metal remaining-thickness checking portion provided adjacent to the grinding-processed layer, sealed by the sealing resin, and having a inclined plane that is inclined with respect to a laminating direction of the grinding-processed layer.
摘要翻译：半导体器件包括半导体芯片和层叠在半导体芯片的一个表面上的研磨处理层。此外，半导体器件包括密封半导体芯片和研磨处理层的密封树脂; 以及与所述研磨处理层相邻设置的密封树脂密封的金属剩余厚度检查部，具有相对于所述研磨处理层的层叠方向倾斜的倾斜面。

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