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1. 发明申请

US20090047757A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090047757A1
公开(公告)日：2009-02-19
申请号：US12253510
申请日：2008-10-17
申请人： Mikio TSUJIUCHI , Toshiaki IWAMATSU , Takashi IPPOSHI
发明人： Mikio TSUJIUCHI , Toshiaki IWAMATSU , Takashi IPPOSHI
IPC分类号： H01L21/336
CPC分类号： H01L29/458 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78609
摘要： In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.
摘要翻译：在SOI衬底中形成的元件之间的隔离部分沟槽隔离的半导体器件中，针对晶体管的源极漏极的电阻降低和泄漏电流的降低。在形成在掩埋氧化膜层（BOX层）上的SOI层中的隔离绝缘层规定的有源区域中形成MOS晶体管。隔离绝缘层是尚未到达BOX层的部分沟槽隔离，源区和漏区包括彼此相互质量数不同的第一和第二杂质离子。

2. 发明申请

US20080203479A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080203479A1
公开(公告)日：2008-08-28
申请号：US12108369
申请日：2008-04-23
申请人： Tetsuya WATANABE , Takashi IPPOSHI
发明人： Tetsuya WATANABE , Takashi IPPOSHI
IPC分类号： H01L29/786
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78615
摘要： In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole of the opposed surfaces between the four source regions in such a manner that the channel region formed under the gate electrode is divided across the channel length. A body-tied region containing N-type impurities relatively high in concentration is arranged in contact with the side surface of the source region opposite to the gate electrode, and the potential of the body region is fixed through the well region from the body-tied region.
摘要翻译：在PMOS晶体管中，源极 - 漏极区域沿着栅极宽度分成四个部分，并且具有四个独立源极区域和四个独立漏极区域的布置的布置。部分沟槽隔离绝缘膜被布置成与四个源极区域之间的整个相对表面接触，使得形成在栅电极下方的沟道区域跨越沟道长度被划分。包含浓度相对较高的N型杂质的身体绑扎区域与源极区域与栅电极相对的侧表面接触，并且身体区域的电位通过身体连接的孔区域固定地区。

3. 发明申请

US20080054414A1 Method of manufacturing semiconductor device having impurity region under isolation region 有权
标题翻译：制造在隔离区域具有杂质区域的半导体器件的制造方法
公开(公告)号：US20080054414A1
公开(公告)日：2008-03-06
申请号：US11907864
申请日：2007-10-18
申请人： Shigenobu MAEDA , Toshiaki IWAMATSU , Takashi IPPOSHI
发明人： Shigenobu MAEDA , Toshiaki IWAMATSU , Takashi IPPOSHI
IPC分类号： H01L23/58 , H01L21/31
CPC分类号： H01L29/78615 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
摘要翻译：在形成NMOS晶体管的源极/漏极区域的情况下，在N + +块区域中的N + +块区域<41>的栅极方向延伸区域抗蚀剂膜<51>防止位于栅极方向延伸区域41a之下的阱区11注入N型杂质。作为高电阻形成区域，其是具有在栅电极9的纵向延伸上注入N型杂质的可能性的阱区域11，可以形成为高电阻形成区域比传统的高电阻形成区域窄。因此，获得具有能够降低体电阻的部分隔离体固定的SOI结构的半导体器件及其制造方法。

4. 发明申请

US20080050864A1 Method of manufacturing semiconductor device having impurity region under isolation region 失效
公开(公告)号：US20080050864A1
公开(公告)日：2008-02-28
申请号：US11907857
申请日：2007-10-18
申请人： Shigenobu MAEDA , Toshiaki IWAMATSU , Takashi IPPOSHI
发明人： Shigenobu MAEDA , Toshiaki IWAMATSU , Takashi IPPOSHI
IPC分类号： H01L21/02
CPC分类号： H01L29/78615 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film prevents a well region located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

5. 发明申请

US20070221995A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070221995A1
公开(公告)日：2007-09-27
申请号：US11672487
申请日：2007-02-07
申请人： Takaya SUZUKI , Takashi IPPOSHI
发明人： Takaya SUZUKI , Takashi IPPOSHI
IPC分类号： H01L23/62
CPC分类号： H01L27/0629 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： The present invention realizes the miniaturization of a semiconductor device. On a first insulation film, an island-like semiconductor layer and a second insulation film which surrounds the semiconductor layer are formed, and resistance elements (for example, poly-silicon resistance elements) which are formed of a conductive film are arranged to be overlapped to an upper surface of the semiconductor layer in plane.
摘要翻译：本发明实现了半导体器件的小型化。在第一绝缘膜上形成围绕半导体层的岛状半导体层和第二绝缘膜，并且由导电膜形成的电阻元件（例如，多晶硅电阻元件）被布置成重叠到半导体层的上表面。

6. 发明申请

US20070105329A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070105329A1
公开(公告)日：2007-05-10
申请号：US11617936
申请日：2006-12-29
申请人： Toshiaki Iwamatsu , Takashi Ipposhi
发明人： Toshiaki Iwamatsu , Takashi Ipposhi
IPC分类号： H01L29/76 , H01L21/8222
CPC分类号： H01L27/0617 , H01L21/76283 , H01L21/84 , H01L27/0629 , H01L27/1203 , H01L27/13 , H01L28/10 , H01L28/20 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.
摘要翻译：多个沟槽隔离膜在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层的表面中设置有SOI层的部分。电阻元件分别形成在沟槽隔离膜上。每个沟槽隔离膜包括穿过SOI层并到达掩埋氧化膜以包括全沟槽隔离结构的中心部分，以及相对的侧部，其每个仅穿过SOI层的一部分并且位于在SOI层上以包括部分沟槽隔离结构。因此，每个沟槽隔离膜包括混合沟槽隔离结构。

7. 发明授权

US07187040B2 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07187040B2
公开(公告)日：2007-03-06
申请号：US11078581
申请日：2005-03-14
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L29/76 , H01L31/113
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

8. 发明申请

US20060289904A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20060289904A1
公开(公告)日：2006-12-28
申请号：US11425072
申请日：2006-06-19
申请人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Takashi Ipposhi
发明人： Mikio Tsujiuchi , Toshiaki Iwamatsu , Takashi Ipposhi
IPC分类号： H01L29/76
CPC分类号： H01L29/458 , H01L21/76283 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78609
摘要： In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.

9. 发明申请

US20060244064A1 Semiconductor device for limiting leakage current 失效
公开(公告)号：US20060244064A1
公开(公告)日：2006-11-02
申请号：US11448827
申请日：2006-06-08
申请人： Takashi Ipposhi , Toshiaki Iwamatsu
发明人： Takashi Ipposhi , Toshiaki Iwamatsu
IPC分类号： H01L27/12
CPC分类号： H01L29/7833 , H01L21/761 , H01L21/76283 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/665
摘要： Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).

10. 发明授权

US07112854B1 Thin-film transistor and method of fabricating the same 失效
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US07112854B1
公开(公告)日：2006-09-26
申请号：US08850631
申请日：1997-05-02
申请人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
发明人： Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Il-Jung Kim , Kazuhito Tsutsumi , Hirotada Kuriyama , Yoshiyuki Ishigaki , Motomu Ukita , Toshiaki Tsutsumi
IPC分类号： H01L29/78
CPC分类号： H01L29/78609 , H01L27/124 , H01L29/41733 , H01L29/458 , H01L29/66757 , H01L29/78618 , H01L29/78624 , H01L29/78639
摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
摘要翻译：提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

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